clex16.in : SRAM Analysis for Back Annotation into SPICE model
This example is a six-transistor, three metal, single poly SRAM cell. The cell consists of four NMOS and two PMOS transistors.
The layout file defines various layers up to metal 3. The rule file exports six new masks, plus CLEVER defines another two masks - *GATE and *CONT. These masks are gates and contacts, which are the NGATE and PGATE regions, plus the two exported contacts. The modified layout and a SPICE netlist of the devices are saved after the original layout file is initialized in the command file and the rule file executed in the command file.
The gate oxide is defined as a separate material, called Gateox, distinct from silicon oxide. Gateox is given a very low (but non-zero) permittivity. As a result, the area calculation of capacitance (i.e. determined by the transistor gate area over the gate oxide and silicon) is very low. This area capacitance of the gate over silicon is accurately calculated in the SPICE model (since only the area and gate oxide thickness are necessary). Since CLEVER calculates the total field solution, it does not distinguish the contribution of the capacitance due to the poly gate over the silicon from either the fringe effects or capacitance with other conducting lines. This methodology of artificially lowering the area capacitance in CLEVER avoids calculating this value twice, once in CLEVER, and once again in the SPICE model.
The geometry of the structure is the idealized Manhattan cross-sections. No advanced lithographic or etch models are used.
This example is also discussed in the CLEVER tutorial in the manual.
To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.
go VictoryProcess Init Layout=clex16.lay Depth=1 Material=Silicon RuleFile=clex16.lmp Electrode Substrate ## Process Description ## ## Trench and Fill ## Etch Material=Silicon Thickness=0.5 Max Mask=AA Deposit Material=Oxide Thickness=0 Max ## Gate Stack ## Deposit Material=Gateox Thickness=0.01 Max Etch Material=Gateox Mask=*GATE reverse Deposit Material=Oxide Thickness=0 Max Deposit Polysilicon Thickness=0.2 Max Etch Material=Polysilicon Mask=poly Electrode Mask=*GATE Material=Polysilicon ## Contact ## Deposit Material=Oxide Thickness=0.4 Max Etch Material=Oxide Mask=cont Reverse ## Stop Source/Drain/Substrate Contacts Shorting to Substrate ## Deposit Material=Gateox Thickness=-0.6 Max ## Named polygons will be converted into electrodes ## Electrode Mask=*CONT Material=Gateox ## Metal 1 ## Deposit Material=Aluminum Thickness=0.6 Max Etch Material=Aluminum Mask=M1 Electrode Mask=M1 Material=Aluminum ## M1/M2 via ## Deposit Material=Oxide Thickness=0.5 Max Etch Material=Oxide Mask=via1 Reverse ## M2 ## Deposit Material=Aluminum Thickness=0.8 Max Etch Material=Aluminum Mask=M2 Electrodes Mask=M2 Material=Aluminum ## M1/M2 via ## Deposit Material=Oxide Thickness=0.6 Max Etch Material=Oxide Mask=via2 Reverse ## M3 ## Deposit Material=Aluminum Thickness=1 Max Etch Material=Aluminum Mask=M3 Electrode Mask=M3 Material=Aluminum Deposit Oxide Thickness=1 Max Save Name=clex16_0 go Clever Init Structure="clex16_0.str" Layout="clex16.lay" map="clex16.lmp" Material Silicon Conductivity=1 Material Material("Gateox") Perm=0.01 ## Parasitic Extraction ## Interconnect Adapt=(0.05,0.02) capsolver=1 Save Spice="clex16.net" quit