clex10.in : Inverter Cell with Lithographic Geometry
Requires: CLEVER
An inverter is one of the most common cells found in layouts. This example contains one inverter cell designed with 4 NMOS and 4 PMOS transistors. It is an illustration of how Clever inserts auxilliary nodes, as in example clex05.in, where necessary into the layout. The back-annotated layout may then be re-plotted in Maskviews.
This example applies lithographic techniques to more accurately simulate the non-uniform barrier layer, formed by the resist after the imaging photolithographic stage. VictoryProcess is called upon once again to simulate the non Manhatton structure creation. The etching process also uses a more physical 87 degree angled side-wall.
This example has been used in the CLEVER Tutorial and more information on it can be found there.
To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.
Input Deck
go victoryprocess
## Process Description ##
Init Layout=clex10.lay Depth=1 material=silicon RuleFile=clex10.lmp
set accuracy=0.005
# Create Gate Mask Photoresist shape
lithography mask=POLY maskcriticalintensity=0.5 maskaperture=0.5 \
maskdefocus=0 wavelength=0.193
# Gate Stack Process Steps
Deposit material=Oxide Thickness=0.25 Max
Deposit material=Polysilicon Thickness=0.3 Max
Etch material=Polysilicon thickness=0.36 angle=87 Mask=POLY_LITHO max \
tolerance=$accuracy
Electrodes mask=POLY material=polysilicon
Electrodes mask=*GATE material=poly
# Create Via 2 Mask Photoresist Shape
lithography mask=VIA2 maskcriticalintensity=0.21 maskaperture=0.5 \
maskdefocus=0 wavelength=0.193 resultimage=via2.str
# Via 2 Process Steps
Deposit material=Oxide Thickness=0.25 Max
Etch material=Oxide Thickness=0.8 Angle=87 Mask=VIA2_LITHO Reverse max \
tolerance=$accuracy
Electrodes mask=*CONT material=Silicon
# Create Metal 1 Photoresist Shape
lithography mask=MET1 maskcriticalintensity=0.5 maskaperture=0.5 \
maskdefocus=0 wavelength=0.193
# Metal 1 Process Steps
Deposit material=Aluminum Thickness=0.25 Max
Etch material=Aluminum Thickness=0.3 angle=87 Mask=MET1_LITHO max \
tolerance=$accuracy
Electrodes mask=MET1 material=Aluminum
# Create Via 3 Photoresist Shape
lithography mask=VIA3 maskcriticalintensity=0.5 maskaperture=0.5 \
maskdefocus=0 wavelength=0.193 resultimage=via3.str
# Via 3 Process Steps
Deposit material=Oxide Thickness=0.25 Max
Etch material=Oxide Thickness=0.3 angle=87 Mask=VIA3_LITHO Reverse max \
tolerance=$accuracy
# Create Metal 2 Photoresist Shape
lithography mask=MET2 maskcriticalintensity=0.5 maskaperture=0.5 \
maskdefocus=0 wavelength=0.193
# Metal 2 Process Steps
Deposit material=Aluminum Thickness=0.5 Max
Etch material=Aluminum Thickness=0.6 angle=87 Mask=MET2_LITHO max \
tolerance=$accuracy
Electrodes mask=MET2 material=Aluminum
# Passivation
Deposit material=Oxide Thickness=0.25 Max
Save Name=clex10_0
## After creating the 3D structure ##
## Perform the Interconnect Analysis ##
go clever
Init Layout="clex10.lay" Map="clex10.lmp" structure="clex10_0.str"
Save Spice="clex10.before.net" Layout="clex10_1.lay"
Interconnect Adapt=(0.04, 0.02)
Save Spice="clex10.net"
quit