March 16, 2021 | 10:00 am – 10:20 am (PST)
This webinar will review the various Silvaco SPICE modeling solutions. This includes a brief overview of our tools, Utmost IV and TechModeler, and of the modeling services that we provide to our customers. We discuss a few of our recent modeling examples for various technologies, including display-related, RF SPICE modeling, and advanced processes.
March 18, 2021 | 10:00 am – 10:30 am (PST)
In this webinar we will cover the capabilities and usage of Victory TCAD Process simulator and explain how materials and simulation parameters can be set, including boundary conditions, which solvers are supported and how to set up different types of simulation.
January 14, 2021 | 10:00 am – 10:20 am (PST)
In this webinar, Sharmistha Sinha and Anand Mishra share their analysis and experience with Cello done at ST on multiple technologies.
December 17, 2020 | 10:00 am – 10:15 am (PST)
In this webinar, we describe Silvaco’s Analog Custom Design solution and how the 2020 release addresses the driving forces of better interoperability, performance, and productivity.
November 12, 2020
Silvaco Inc., a leading supplier of EDA software and design IP, today announced that it has completed the acquisition of the memory compiler technology and standard cell libraries of Dolphin Design SAS.
In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation.
In this paper the critical design features of a SiC superjunction trench MOS device were optimized using CAD to obtain a high breakdown voltage while minimizing any unnecessary increase in channel resistance.
Conductive Bridge Random Access Memory (CBRAM) is a non-volatile memory device technology that can operate by consuming very low power. Another advantage of the CBRAM devices is its ability to be easily integrated into conventional back-end-of-line CMOS processes [1].
The qualification of GaN power high-electron-mobilitytransistors (HEMTs) must consider the device ruggedness against out-of-SOA (safe operating area) events [1- 3].