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Simulate 40X Faster with SmartSpice HPP

As technology advances and the complexity of circuit designs continues to grow, analog simulation can easily become the bottleneck for design verification. In order to cope with this increasing pressure on the simulator’s performance, SmartSpice provides a scalable simulation engine: HPP (High Performance Parallel). 

In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation. 

Attendees will have a better understanding of how SmartSpice HPP works and how to use it in order to provide fast and accurate transient simulations on a variety of designs, from medium- to large-size circuits, either pre- or post-layout. We will also demonstrate multiple usage modes, to show that SmartSpice HPP can not only be up to 8x more scalable than regular SmartSpice, but that it can also be up to 40x faster, while still keeping acceptable accuracy. 


Jody Matos

Dr. Jody Matos is Ph.D. Computer Scientist who is passionate about research and development of software and hardware designs. Currently, he is a Senior Manager at Silvaco, Inc, where he has been managing leading-edge R&D and business-related projects for EDA tools. His current tasks are mainly related to circuit simulation and analyses on analog, digital and mixed-signal IC designs. Dr. Matos joined Silvaco in 2018 as part of the acquisition of Nangate, where he researched and developed EDA tools for layout automation and standard cell library characterization.
Dr. Matos received a Ph.D. degree in computer science from the Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, and a M.S. degree in microelectronics from the same institution. He has co-authored 30+ research papers and patent applications that mix knowledge of both computer science and microelectronics. Dr. Matos has also served on technical committees of several international conferences in the fields of design automation.


Analog circuit designers, CAD engineers in the circuit simulation field, design engineers, and students new to circuit simulation.

When: November 17, 2020
Where: Online
Time: 10:00am-10:30am-(PST)
Language: English