Simulate 40X Faster with SmartSpice HPP
As technology advances and the complexity of circuit designs continues to grow, analog simulation can easily become the bottleneck for design verification. In order to cope with this increasing pressure on the simulator’s performance, SmartSpice provides a scalable simulation engine: HPP (High Performance Parallel).
In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation.
Attendees will have a better understanding of how SmartSpice HPP works and how to use it in order to provide fast and accurate transient simulations on a variety of designs, from medium- to large-size circuits, either pre- or post-layout. We will also demonstrate multiple usage modes, to show that SmartSpice HPP can not only be up to 8x more scalable than regular SmartSpice, but that it can also be up to 40x faster, while still keeping acceptable accuracy.
WHO SHOULD ATTEND:
Analog circuit designers, CAD engineers in the circuit simulation field, design engineers, and students new to circuit simulation.
When: November 17, 2020