In the following video, I interview Silvaco customer Randy Caplan of Silicon Creations from the show floor at DAC 2019, in Las Vegas, about the latest trends and challenges for nanometer IC design success. He talks about using a suite of Silvaco design tools down to the latest 5 nm silicon process nodes. A full ranscript of the conversation is below, as well.

library of digital standard cells implements both Boolean logic and sequential storage functions. These foundation IPs are used extensively and repeatedly within application specific integrated circuits (ASICs), field programmable arrays (FPGAs), microprocessors and system-on-chip devices (SOCs).