Good News – The Silvaco Analog Custom Design Flow

December 17, 2020 | 10:00 am – 10:15 am (PST) In this webinar, we describe Silvaco’s Analog Custom Design solution and how the 2020 release addresses the driving forces of better interoperability, performance, and productivity.

Silvaco Presents at 13th International MOS-AK Virtual Workshop, Dec. 10 – 11

The 13th International MOS-AK Workshop will be hosted virtually on December 10 and 11, 2020, and Silvaco R&D will be presenting. The MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Customer Interview: Why I Rely on SmartSpice

Martin Mallinson is an experienced analog circuit designer with multiple patents. Over his 40-year career, his audio designs have been used in millions of smartphones.  Martin spoke with Graham Bell about why SmartSpice is different from other analog simulators and how he relies on its interactivity, speed, and precision for his analog design work.

Simulate 40X Faster with SmartSpice HPP

As technology advances, the complexity of circuit designs is continuously growing, whereas the design cycles become even shorter. Consequently, circuit simulation can easily become the bottleneck for design verification. An analog simulator, therefore, must deal with a larger number of advanced devices, while still maintaining the same level of accuracy for a given simulation time.In order to cope with this increasing pressure on the simulator’s performance, SmartSpice has introduced a new simulation engine: HPP (High Performance Parallel). SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits.

Simulate 40X Faster with SmartSpice HPP

In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation. 

Improvement of Parasitic Capacitance Extraction Rules for Large-Scale Layout and Its Accuracy Verification Method

September 17, 2020 | 13:00 – 13:30 (JST) The accuracy of rule-based full-chip parasitic capacitance extraction tools including Silvaco's Hipex is highly dependent on the description of the rule files.

Model Extraction Flow with Utmost IV for Vertically Stacked Nanosheets Using the Leti-NSP Model

July 30, 2020 | 10:00 am – 10:30 am (PDT) This webinar will provide a discussion of common methods used to secure an AMBA-based hardware and software system design.

Using SmartSpice Compact Models

June 11, 2020 | 10:00 am – 10:30 am (PDT) This webinar will provide a guide to developing Compact Models in SmartSpice to achieve optimal simulation performance. You will learn how models are used in SmartSpice and best practices when constructing a custom Verilog-A model.

Machine Learning in the EDA-Specific Domain – 20 Years in the Making

June 25, 2020 | 10:00 am – 10:30 am (PDT) This webinar will review these new approaches and how they are applied to different applications. Example ML-based EDA tools form Silvaco will be presented to illustrate what have been achieved.