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Robust SPICE Modeling with Verilog-A: Principles and Practical Techniques

Insufficient robustness of models in SPICE circuit simulators may lead to a poor convergence, simulation failures and finally an unreliable or incorrect circuit design. Implementation of these compact models, including the responsibility to ensure robust behavior, were traditionally left to the expertise of EDA vendors. However, with the introduction and wide adoption of Verilog-A as a model coding language in analog circuit simulators, the power of the model implementation is now available to the circuit designers and SPICE circuit simulator users. It has also brought an unaccustomed responsibility to circuit designers and model developers to ensure robustness of the implemented model. The main goal of this webinar is to present an expert guidance for robust coding of SPICE compact models in Verilog-A.

What attendees will learn:

  • Basic principles and best practices for ensuring robustness of SPICE compact models coded in Verilog-A.
  • How to avoid floating point exceptions and real number related issues in model evaluation and hidden evaluation of model code derivatives.
  • How to provide required continuity of a model behavioral description using smoothing, limiting and transition functions.
  • Practical techniques for improving SPICE convergence robustness in circuit simulations with Verilog-A models.


Dr. Slobodan MijalkovicDr. Slobodan Mijalkovic is a Senior R&D Engineer at Silvaco specialized in compact model development and implementation in circuit simulation tools. Before joining Silvaco, he was a Principal Researcher at Delft University of Technology in the Netherlands, where he has led a team for standardization of the Mextram bipolar transistor model with Compact Model Coalition (CMC). He is a member of IEEE EDS Compact Modeling Committee.

When: June 25, 2019
Where: Online
Time: 10:00am-11:00am-(PST)
Language: English


Circuit designers and model developing experts in academia and industry who are coding SPICE compact models in the Verilog-A language.