• Simulation Standard Technical Journal

Simulation Standard

Technical Journal

A Journal for Process and Device Engineers

Measure CJSWG (CJGATE) Capacitance using UTMOST III

For the UTMOST III versions greater than 17.2.0.R, the UTMOST users can measure the CJSWG (CJGATE) capacitance using the "CJ/CJSW" routine. The CJ/CJSW routine in MOS technology has been modified to measure the CJSWG (Peripheral portion of the junction capacitance under the gate) capacitance.

Cross-Sectional Viewer in Expert

Cross-Sectional Viewer is a tool within Expert to simulate the cross sectional view of ICs along an arbitrary drawn cut-line on the layout. Cross-sectional Viewer is a link between the layout and the resulting device. It allows the designer to examine cross-sections of the device being designed. Cross-sectional drawings are useful for understanding design rules, parasitic coupling and other design and fabrication problems.

Expert: Recent Improvements in Hierarchical Layout Inspection

The functionality of several features of Expert layout editor has been enhanced to deal with hierarchical layouts in more convenient ways.

Applicability of Distance Computation for Graphs to LVS Discrepancy Analysis

An important step in electronic circuit design is layout versus schematic verification (LVS)

Expert Hints, Tips, and Solutions: Object Scripting, Layer Color Palette, Big Measurements

Q: Often I need to measure big objects. It order to position the ruler precisely I must zoom in at one end, zoom out that zoom again in at the other end. Is it possible too make this operation more convenient? For example, can I start the measurement in one window and finish it in another one?

Yield Analysis and Performance Optimization Using FastBlaze and SPAYN

In previous Simulation Standard articles (Nov 97 & Nov 98) FastBlaze has been presented as a new, highly efficient approach to simulating advanced HEMTs and MESFETs. Conventional device simulators often suffer from slow execution times, leading to a trade off between mesh density and physical model complexity against CPU run time and convergence. This requires engineers to compromise accuracy to achieve a reasonable throughput.