• Analog Custom Design & Analysis Examples

opt_ex20 : PSP MOSFET Model Extraction

Requires: Utmost IV, SmartSpice, SmartView

Minimum Versions: Utmost IV 2.7.1.R, SmartSpice 4.30.0.R, SmartView 2.34.0.R

This example describes how to extract a standard PSP model. To extract a model which is scalable with geometry, multiple different device sizes must be included. In this example, seven device geometries are included.

The project file opt_ex20.prj and the data file opt_ex20.uds for this example should be loaded into your database. When opened, the project will look as shown in opt_ex20_project.png .

Preliminary information

The PSP model allows independent parameters to describe the oxide thickness of the gate and overlap regions (model parameters TOXO and TOXOVO, respectively). In order to enforce equal values for these two parameters, one can assign them to the same netlist parameter (PTOX) and optimize the netlist parameter instead: opt_ex20_model_card.png and opt_ex20_netlist_parameters.png .

The extraction and optimization sequence, which fully automates the extraction of this PSP model, has sixteen sections. The objective of each section is to isolate a device characteristic and then to optimize only those model parameters which account for this device behavior. Some of the model parameters are optimized in multiple sections for better fitting.

The first 6 sections are used for extracting gate and overlap capacitance parameters from capacitance data. If this data is not available, one can skip these steps and start the sequence directly from step 7 instead.

Before starting the optimization sequence, the following device parameters are defined in the model library.

  • TOXO: Gate oxide thickness (uses the value of netlist parameter PTOX, as noted above)
  • TOXOVO: Overlap oxide thickness (uses the value of netlist parameter PTOX, as noted above)
  • TR: Nominal room temperature

Section 1 : cgg

This section performs a preliminary extraction of the oxide thickness based on Cgg versus gate voltage data. The extracted value is stored in the PTOX netlist parameter, as shown in opt_ex20_01.png .

Section 2 : cgg

This section uses Cgg versus gate voltage data to optimize the gate capacitance parameters. The following parameters are optimized.

  • PTOX (Netlist parameter) Gate and overlap oxide thickness
  • VFBO Flat-band voltage at TR
  • DPHIBO Surface potential offset
  • NSUBO Substrate doping

After this step has been completed, the fit to measured data will be as shown in opt_ex20_02.png .

Section 3 : cgd

This section performs a preliminary extraction of the overlap region length using Cgd versus gate voltage data. The extracted value is stored in the LOV model parameter, as shown in opt_ex20_03.png .

Section 4 : cg_overlap

This section optimizes the overlap capacitance parameters using Cgd and Cgc versus gate voltage data. The following model parameters are optimized.

  • LOV Overlap capacitance region length
  • NOVO Effective doping of overlap region

After this step has been completed, the fit to measured data will be as shown in opt_ex20_04.png .

Section 5 : cgg

This section refines the parameters previously extracted in section #2 using Cgg data. The following model parameters are optimized.

  • PTOX (Netlist parameter) Gate and overlap oxide thickness
  • VFBO Flat-band voltage at TR
  • DPHIBO Surface potential offset
  • NSUBO Substrate doping

After this step has been completed, the fit to measured data will be as shown in opt_ex20_05.png .

Section 6 : cg_all

This section refines the gate and overlap capacitance parameters extracted in the previous sections. The following model parameters are optimized.

  • PTOX (Netlist parameter) Gate and overlap oxide thickness
  • VFBO Flat-band voltage at TR
  • DPHIBO Surface potential offset
  • NSUBO Substrate doping
  • LOV Overlap capacitance region length
  • NOVO Effective doping of overlap region

After this step has been completed, the fit to measured data will be as shown in opt_ex20_06.png .

Section 7 : idvglin_large_rt

This section optimizes the I-V parameters for wide and long channel devices. The data in this section is the drain current versus gate voltage characteristic in the linear region and at room temperature. The following model parameters are extracted.

  • VFBO Flat-band voltage at TR
  • DPHIBO Surface potential offset
  • NSUBO Substrate doping
  • CTO Interface states factor
  • UO Zero-field mobility at TR
  • THEMUO Mobility reduction exponent at TR

After this step has been completed, the fit to measured data will be as shown in opt_ex20_07.png .

Section 8 : idvglin_large_rt

This section represents a rerun of the previous section in order to achieve a better fitting for the wide and long channel device drain current in the linear region.

After this step has been completed, the fit to measured data will be as shown in opt_ex20_08.png .

Section 9 : idvglin_warray_rt

The narrow width parameters are now extracted using data from devices with various channel widths and with a long channel value. The following model parameters are extracted.

  • WOT Effective channel width reduction per side due to lateral diffusion
  • VFBW Width dependence of flat-band voltage

After this step has been completed, the fit to measured data will be as shown in opt_ex20_09.png .

Section 10: idvglin_larray_rt

In this section, the parameters for short channel effects are optimized using devices of multiple lengths and wide channel value. The following model parameters are extracted.

  • LAP Effective channel length reduction per side due to lateral diffusion
  • VFBO Flat-band voltage at TR
  • VFBL Length dependence of flat-band voltage
  • DPHIBO Surface potential offset
  • NSUBO Substrate doping
  • DNSUBO Effective doping bias-dependence parameter
  • CTO Interface states factor
  • CTL Length dependence of interface states factor
  • FOL1 First order length dependence of short channel body-effect
  • UO Zero-field mobility at TR
  • THEMUO Mobility reduction exponent at TR
  • RSW1 Source/drain series resistance for a channel width WEN
  • RSBO Back-bias dependence of RS
  • RSGO Gate-bias dependence of RS

After this step has been completed, the fit to measured data will be as shown in opt_ex20_10.png .

Section 11 : idvglin_rt

This section refines the previously extracted I-V parameters using devices of multiple channel lengths and widths in the linear region and at room temperature ID-VG data.

After this step has been completed, the fit to measured data will be as shown in opt_ex20_11.png .

Section 12 : idvglin_large_t

This section extracts the model parameters for the large geometry drain current versus gate voltage linear temperature measurements. The following parameters are optimized.

  • STVFBO Temperature dependence of VFB
  • STBETO Temperature dependence of BETN
  • STTHEMUO Temperature dependence of THEMU

After this step has been completed, the fit to measured data will be as shown in opt_ex20_12.png .

Section 13 : idvglin_t

Now we select all of the device geometries at temperature for the linear drain current versus gate voltage characteristics and optimize the following parameters.

  • STVFBO Temperature dependence of VFB
  • STVFBL Length dependence of STVFB
  • STVFBW Width dependence of STVFB
  • STBETO Temperature dependence of BETN
  • STTHEMUO Temperature dependence of THEMU
  • STRSO Temperature dependence of RS

After this step has been completed, the fit to measured data will be as shown in opt_ex20_13.png .

Section 14 : idvd_rt

The first 13 sections concentrated only on the linear regions drain current versus gate voltage for each of the different geometries. This section will use the saturation region drain current and conductances versus drain voltage data for all device geometries. The following parameters are optimized.

  • CFL Length dependence of DIBL
  • THESATO Velocity saturation parameter at TR
  • ALPL CLM pre-factor length dependence
  • ALP1L1 CLM enhancement factor above threshold length dependence
  • ALP2L1 CLM enhancement factor below threshold length dependence
  • VPO CLM logarithmic dependence parameter

After this step has been completed, the fit to measured data will be as shown in opt_ex20_14.png .

Section 15 : idvgsat_rt

This section verifies the fitting of the saturation drain current versus gate voltage characteristics with back bias. No parameters need to be optimized. The fit to measured data will be as shown in opt_ex20_15.png .

Section 16 : idvd_t

This section will extract the parameters for the saturation drain current versus drain voltage characteristics versus temperature. The parameters to be optimized are as follows.

  • STTHESATO Temperature dependence of THESAT

After this step has been completed, the fit to measured data will be as shown in opt_ex20_16.png .

The sequence may be run multiple times in order to improve the fit of the model to the measured data as necessary.

When complete, the model card can then be exported into an external model library file as shown in the output file opt_ex20.lib.

Additional Info:
Files
opt_ex20.lib
opt_ex20.uds
Graphics
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