• Analog Custom Design & Analysis Examples

opt_ex15 : Three Terminal R3_CMC Resistor Model Extraction

Requires: Utmost IV, SmartSpice, SmartView

Minimum Versions: Utmost IV 1.11.0.R, SmartSpice 4.10.2.R, SmartView 2.28.2.R

This example describes how to extract a three terminal r3_cmc model including temperature coefficients and parasitic parameters. This model is designed to model lightly doped resistors, such as well resistors and in this case we will model an nwell resistor.

The project file opt_ex15.prj and the data file opt_ex15.uds for this example should both be loaded into your database. When opened, the project will look as shown in opt_ex15_01.png .

There are five sections in the extraction sequence. The first three sections deal with the main resistor at room temperature, with back bias and then with temperature effect. The last two sections deal with the parasitic diode current and capacitance to the third terminal. The objective of each section is to isolate a device characteristic and then to extract or optimize only those model parameters which account for this device effect.

The first section, selects the resistor measurement at the nominal temperature, as shown in opt_ex15_02.png . From this single dataset, we pre-extract a sheet resistance value. This is done by the extraction 'rsh' which is defined as shown in opt_ex15_03.png . The extraction setup, also called 'rsh', is used to select the extraction to be performed on the single dataset and also defines where to write the result as shown in opt_ex15_04.png . In this case, the extraction called 'rsh' is performed and the result is written into the model parameter RSH of the model NWRES into the optimized column. Then we optimize the sheet resistance parameter again along with parameters describing the velocity saturation of the device. Once this optimization has been run, the measured vs simulated IV characteristics are displayed in the viewer as shown in opt_ex15_05.png .

The second section deals with the change in the resistance due to the bias effect from the third terminal. For an nwell resistor, with a pbulk region, negative bias on the ptype third terminal will reverse bias the junction and extend a depletion region into the nwell which will pinch off the resistor. This will increase the resistivity of the nwell resistor layer. For this optimization we will use datasets at the nominal temperature, but with differing back biases. Once this optimization has been run, the measured vs simulated characteristics are displayed in the viewer as shown in opt_ex15_06.png .

The third section deals with the temperature coefficients. One resistor has been measured at four temperatures and the dataset subset definition is as shown in opt_ex15_07.png . The first and second order temperature coefficients TC1 and TC2 are optimized. Once this optimization has been run, the measured vs simulated IV and extracted characteristics are displayed in the viewer as shown in opt_ex15_08.png .

The fourth section deals with the forward diode parasitic current optimization. Note that the model does not account for the roll off in current with higher forward biases, however, it is not intended that this junction be forward biased during normal resistor operation. After optimization the measured vs modeled parasitic current characteristics are as shown in opt_ex15_09.png .

Finally in the fifth section, the parasitic reverse junction capacitance of the n-well resistor to the p bulk is optimized. After optimization the measured vs modeled characteristic will be as shown in opt_ex15_10.png .

The model card can then be exported into an external model library file as shown in the output file opt_ex15.lib.

Additional Info:
Files
opt_ex15.lib
opt_ex15.uds
Graphics
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