009_mos_prop_delay : Propagation delay
Requires: SmartSpice & Smartview
Minimum Versions: SMARTSPICE 4.6.5.R
The input deck uses a 32 input NAND gate with .TRAN analysis to demonstrate the rubberbanding of a complete block rather than a individual device.
Input Files
rubberband_example_09.in
*32-INPUT NAND GATE ( 132 MOSFETS ) * SSPICE INVESTIGATES THE DEPENDENCE OF THE PROPAGATION DELAY * OF THE CICUIT OUTPUT SIGNALS ON TWO MOSFET MODEL PARAMETERS * .SUBCKT NAND 1 2 3 M1 3 1 VDD VDD MODP W=10UM L=3U AS=100P AD=100P M2 3 2 VDD VDD MODP W=10UM L=3U AS=100P AD=100P M3 3 1 6 0 MODN W=10UM L=3U AS=100P AD=100P M4 6 2 0 0 MODN W=10UM L=3U AS=100P AD=100P .ENDS NAND .SUBCKT NOR 1 2 3 M1 6 1 VDD1 VDD1 MODP W=10UM L=3U AS=100P AD=100P M2 3 2 6 VDD1 MODP W=10UM L=3U AS=100P AD=100P M3 3 1 0 0 MODN W=10UM L=3U AS=100P AD=100P M4 3 2 0 0 MODN W=10UM L=3U AS=100P AD=100P .ENDS NOR .SUBCKT INV 1 2 M1 2 1 VDD2 VDD2 MODP W=10UM L=3U AS=100P AD=100P M2 2 1 0 0 MODN W=10UM L=3U AS=100P AD=100P .ENDS INV .SUBCKT INP8 11 12 10 X1 11 12 3 NAND X2 12 12 4 NAND X3 12 12 5 NAND X4 12 12 6 NAND X5 3 4 7 NOR X6 5 6 8 NOR X7 7 8 9 NAND X8 9 10 INV .ENDS INP8 .GLOBAL VDD VDD1 VDD2 *......... CIRCUIT ......................................... VDD VDD 0 DC 5.0V VDD1 VDD1 0 DC 5.0V VDD2 VDD2 0 DC 5.0V V1 11 0 PULSE (0 5 2NS 1NS 1NS 20NS 40NS) V2 12 0 PULSE (0 5 2NS 1NS 1NS 60NS 120NS) V3 13 0 DC 5.V X1 11 12 1 INP8 X2 13 12 2 INP8 X3 13 12 3 INP8 X4 13 12 4 INP8 X5 1 2 5 NAND X6 3 4 6 NAND X7 5 6 7 NOR CL 7 0 20.FF .MODEL MODP PMOS (LEVEL=49 UO=275 CBD=40.0FF + PB=0.8 PHI=0.6 GAMMA=0) .MODEL MODN NMOS (LEVEL=49 RS=10 rd=10 UO=550 CBD=40.0FF + PB=0.8 PHI=0.6 GAMMA=0) *......... TRAN, MEASURE and MODIF COMMANDS ................. .TRAN 1NS 80NS from_step=2n 67n 10n to=78ns .save v(7) v(5) .options nomod numdgt=15 .END
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