• Parasitic Extraction Examples

    Utmost IV Examples

16 : Using Different Methods of Parasitic Capacitance Extraction for Selected Regions (Mix & Match)

Minimum Required Versions: Expert 5.2204.3.C, Hipex 3.8.8.R

This example demonstrates running Hipex Parasitic Capacitance Extraction using VictoryRCx and Stellar Field Solvers for different areas of the same layout, and combining the results into common netlist. This technique is nicknamed "Mix & Match Extraction". It provides opportunity to select (non-overlapping) rectangular blocks on layout, and assign different extraction solvers to process different blocks and the rest of layout. Currently, Hipex supports 3 different solvers:

- Rule-based (heuristical imitation of field solving)

- VictoryRCx (Finite Element Method)

- Stellar (Boundary Element Method).

The functionality is available for Linux only.

1: Start Expert, load GDS layout

Run Expert Layout Editor.

Choose File->Import... . In appeared "Import Project" dialog:

- select GDS II in "File type" control;

- choose mm_exmp.gds file using dialog's file browser;

- choose technology file mm_exmp.tcn using "Technology" control;

- click "Open" button;

- choose cell array_of_pixel2_3x3 to open for extraction.

The sketch of layout (3x3 matrix of TFT cell) is shown on Figure1

2: Load Extraction Settings.

Load settings from mm_exmp.lpe file by choosing Verification->Extraction->Setup... and pressing Load button located at the bottom of appeared dialog.

3: Setting Mix&Match Blocks and Extraction Modes.

To provide usage of Stellar solver for the rest of layout (not covered by Mix&Match blocks), make sure Stellar radio button is ON in Field Solver group of Parasitic Extraction (Capacitance) tab from Layout Parameter Setup dialog, as shown on Figure2 ,and Boxes radio button is ON in Decomposition group with the values specified: SizeX=200, VicinityX=40, SizeY=200, VicinityY=40 (this provides splitting external part of layout into 9 boxes to accelerate Stellar performance).

Inspect Mix-and-Match group. Verify that it is activated (checked) with 2 blocks specified, and using parameters as depicted on Figure2. Both blocks are set to use VictoryRCx simulator, but for second block the non-default option CAPsolver=1 is chosen (boosting performance, though with occasional convergence problems). To assure this assignment (CAPsolver=1), press at "Options" field in second row, and observe "VictoryRCx C-extraction settings" group in appeared dialog (see Figure3 ). The chosen Mix&Match blocks are shown on Figure4 .

Also, verify capacitance mapping (layers Gate, ITO, SD, via, M4 to be mapped ) and mapping of masked dielectric layers (layers Passivation, Via, OxideGate, NIP, aSi, IMDx to be selected) to ensure proper mask usage in process description.

3: Choosing Versions of Utilized Programs.

For variety of extraction settings, Hipex can call executables of VictoryRCx,DeckBuild,VictoryProcess,VictoryMesh to provide simulations and structure build.

Check that compatible (with Hipex) versions of DeckBuild(5.2.12.R or newer), VictoryProcess(7.55.1.C or newer),VictoryMesh (1.7.4.C or newer) and VictoryRCx (1.0.7.R or newer) are installed.

There is (optional) possibility to choose particular versions of abovementioned programs (otherwise, default versions of installed software to be called).

VictoryRCx version can be assigned using appropriate field in Field Solver group of Parasitic Extraction (Capacitance) tab from Layout Parameter Setup dialog (see Figure2).

To assign versions of other programs: Open Technology tab of LPE Setup. The desirable versions of DeckBuild, VictoryProcess,VictoryMesh can be specified in Process simulation setup section (see Figure5 ).

4: Performing extraction.

Run netlist extraction Verification->Extraction->Hipex Net->Run Run capacitance extraction Verification->Extraction->Hipex C->Run Press Open Netlist button to view capacitance netlist.

Input Files
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