• Parasitic Extraction Examples

    Utmost IV Examples

15 : Domain Decomposition in Hipex Parasitic Capacitance Extraction

Minimum Required Versions: Expert 5.2204.3.R, Hipex 3.8.7.R

This example demonstrates running Hipex Parasitic Capacitance Extraction in Domain Decomposition mode using Field Solvers. The functionality is available for Linux only.

The layout decomposition is used in the both solver engines and in the 3D structure builder to process layouts of large size. Two ways of decomposition are supported by Hipex for parasitic capacitance extraction:

  • Stripe decomposition
  • Box decomposition

Hipex forms a set of overlapped partial layouts (original stripes/boxes extended with vicinities, and vicinity areas themselves) to build a series of virtual 3D structures (see Figure1 ). These structures are simulated separately, and then results are combined (using proprietary non-duplicating technique) to produce parasitic capacitors for the whole layout.

Parallel computations are used for the both 3D structure building (by running simultaneously multiple instances of Victory Process) and for Field Solver calculations (by running simultaneously multiple instances of Victory RCx or using multithreading in Stellar solver).

Domain decomposition shows promising results for Field Solver capacitance extraction. Without noticeable sacrifice of accuracy, it dramatically increases the performance of extraction. Decomposition is a way to obtain accurate extraction for layouts too big in size to be processed in one piece.

We will demonstrate domain decomposition on 6 by 6 pixels non-planar TFT layout (see Figure2 ).

1: Start Expert

Run Expert layout editor (either with the command "expert &" or by clicking the "Expert" icon).

2: Load GDS file

Choose File->Import... menu command. In appeared Import Project dialog:

  • select GDS II in the File type control;
  • choose the array_of_pixel2_6x6.gds file using dialog's file browser;
  • choose technology file techfiles/hipex/tft.tcn using the Technology control;
  • click the Open button;
  • choose the array_of_pixel2_6x6 cell to open for extraction.

3: Load Extraction Settings

Select Verification->Extraction->Setup command to open the "Layout Parameter Extraction Setup" dialog. Press the Load button, and choose the array_of_pixel2_6x6_240_300_50_50.lpe file to load required extraction settings.

4: Set device directory

Before performing the extraction of the devices with all the netlist parameters, the user needs to set the proper path to the LISA generic device extraction file. Select Setup->Technology->Device Path Setup command to open the "Device Path Setup" dialog. Specify the <...>/techfiles/hipex directory name in the LISA files directory control and press the Set button.

5: Verify parasitic capacitance extraction settings in Domain Decomposition mode

  • Make sure the techfiles/pex/tft_process__m.in process and the techfiles/pex/tft_materials__m.in materials files are specified in the Process file and Materials file edit lines in the "Technology" tab of the "LPE Setup" dialog (see Figure3 ).
  • Make sure the appropriate versions of DeckBuild, Victory Process and Victory Mesh are specified (if needed) in the Process simulation setup section in the "Technology" tab of the "LPE Setup" dialog (see Figure3 ).
  • Verify capacitance mapping and mapping of masked dielectric layers in the "Parasitic Extraction (Capacitance)" tab of the "LPE Setup" dialog to ensure proper mask usage in process description (see Figure4 ).
  • Make sure the Boxes radio button is turned on and the appropriate values of Size and Vicinity settings are specified in the Decomposition group box in the "Parasitic Extraction (Capacitance)" tab of the "LPE Setup" dialog (see Figure5 ).
  • Make sure the Victory RCx radio button is turned on and the appropriate version of Victory RCx is specified (if needed) in the Field Solver button group in the "Parasitic Extraction (Capacitance)" tab of the "LPE Setup" dialog (see Figure6 ).
  • Specify the extraction parameters in the "Victory RCx Field Solver C-extraction" tab of the "LPE Setup" dialog (see Figure7 ).

6: Performing extraction.

First, run netlist extraction with Verification->Extraction->Net->Run command from the main Expert window. Then, run parasitic capacitance extraction with Verification->Extraction->C->Run command. Press the Open Netlist button to view capacitance netlist.

Additional Info:
Input Files
tft.tcn
run_c.lisa
array_of_pixel2_6x6_opt.lisa
array_of_pixel2_6x6_net_cmd.lisa
array_of_pixel2_6x6_victoryrcx_c_cmd.in
tft_process__m.in

tft_process__m.in

											go victoryp
init depth=10 oxide GasHeight=10 separate.layers

# Metal gate
deposit material=aluminum_m thickness=0.12 max
mask "Gate"
etch material=aluminum_m thickness=0.12 max
strip resist
electrodes "Gate"  material=aluminum_m

# Gate Oxide
deposit material=SiN_m thickness=0.15 conformal

# Active Amorphous Silicon
deposit material=aSi_m thickness=0.033 conformal
mask "aSi"
etch material=aSi_m max
strip resist


# Nitride Hard Mask
deposit material=SiN_m thickness=0.135 conformal

# Source-Drain Contacts
deposit material=Cr_m thickness=0.12 conformal
mask "SD"
etch material=Cr_m max
strip resist
electrodes "SD"  material=Cr_m

# NIP
deposit material=t_silicon_m thickness=1.8 conformal
mask "NIP"
etch material=t_silicon_m max
strip resist

# ITO
deposit material=ITO_m thickness=0.06 conformal
mask "ITO"
etch material=ITO_m max
strip resist
electrodes "ITO"  material=ITO_m

# IMDx
deposit material=SiON_m thickness=2.072 conformal
mask "IMDx"
etch material=SiON_m max 
strip resist


# Top Metal
deposit material=M4aluminum_m thickness=0.646 conformal
mask "M4"
etch material=M4aluminum_m max
strip resist
electrodes "M4" material=M4aluminum_m

# Passivation
deposit material=Passiv_m thickness=2.25 max


# Via
##mask "Via" reverse
##etch material("Passiv") max
##strip resist

save name=""
tft_materials__m.in

tft_materials__m.in

											material  material("aluminum_m")   conductivity=376676 
material  material("aSi_m")   permittivity=7.514 
material  material("Cr_m")   conductivity=5000
material  material("ITO_m")   conductivity=5000
material  material("Passiv_m")  permittivity=9.225
material  material("SiN_m")  permittivity=6.21
material  material("t_silicon_m")  permittivity=16.5
material  material("SiON_m")  permittivity=7.82
material  material("M4aluminum_m") conductivity=5000
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