Logic Gate Recognition

005 : Logic Gate Recognition

Minimum Required Version: Guardian LVS 4.8.36.R

Guardian LVS recognizes primitive logic gates before the netlist comparison. It recognizes not only simple logic gates such as NAND, NOR, and INV, but also complex gates such as AOI and OAI. It allows those logic gates with multiple terminals, such as NAND2, NAND3, NAND4, and so on.

To use this feature, a check box Logic gates in the Models page of the Project Settings dialog should be checked. And also, the net names for power and ground should be specified in Nets/Instances page in the same dialog.

Guardian LVS reports to its log file how many logic gates are found in the specified netlists for the comparison. Those logic gates are treated like other primitive devices in the SPICE netlist format. See an example of the log file with logic gate recognition in CMOS_PFD_lvs.log.

In this report, it is easier to find that a NOR gate existing in the second (layout) netlist doesn't exist in the first (schematic) one, and to guess that one of the NAND gates may be replaced with this NOR gate.

The actual operation steps required to check the command behaviors are as follows:

1) Start Guardian LVS in the GUI mode.

2) Run the Setup->Project Settings command to show the Project Settings dialog.

3) Click the Reset button in the Project Settings dialog.

4) Select the check box Input Files in the General page, and set the following netlists as #1 and #2 netlists:

#1 : CMOS_PFD_lvs.net (schematic netlist)

#2 : CMOS_PFD_hier.spice (layout netlist)

(see lvs_example_05_1.png ).

5) Click the OK button in the Project Settings dialog.

6) Select Action->Run Lvs in the Guardian LVS menu bar. The netlist comparison will be executed, and the resultant log file will appear in the Guardian LVS window. In the log file, only primitive devices will be listed (see lvs_example_05_2.png ).

7) Run the Setup->Project Settings command again, and open the Nets/Instances page (see lvs_example_05_3.png ).

8) Set VDD as a power net and GND as a ground net for the both input netlists.

9) Open the Models page in the same dialog, and click Logic gates for MOS devices (see lvs_example_05_4.png ).

10) Close the Project Settings dialog with the OK button, and run LVS again. The new log file will appear in the Guardian LVS window, in which some logic gates are found for the netlist comparison (see lvs_example_05_5.png ).