• Analog Custom Design & Analysis Examples

    Analog Custom Design & Analysis Examples

005_rect_enclose : Check VIAS on End of Wires

Minimum Required Version : Expert 4.14.0.R, Guardian 4.14.0.R

This command is required for DRC rules for processes of 90nm or below. In former processes, the enclosure of a contact/via by a metal was measured by a single InDistance command. But recent nanometer processes require different contact/via spacing values for the side of the wire, and for the end of the wire.

Here is an example of Rect_Enclose:

   Rect_Enclose: Layer1=VIA,Layer2=METAL1,LayerR=&V1_M1_Bad,
                 good=(0.075um Opposite, 0.025um Opposite,
                       0.075um Opposite, 0.025um Opposite);
 

In this case, the enclosure between VIA and the side of METAL1 wire should be more than or equal to 0.025 micron, and another one between VIA and the end of METAL1 wire should be more than or equal to 0.075 micron.

The actual operation steps to check the command behaviors are as follows:

1) Start Expert .

2) Run File->Open , load the project file guardian_example_24.eld , and then open the top cell. It contains some METAL1 wires and VIA rectangles.

3) Run Verification->DRC->DRC Script Panel , and then File->Open in the script panel to load the sample DRC rule file guardian_example_24.dsf.

4) Run the loaded DRC script by DRC->Run in the DRC script panel.

5) From Expert's main window, run Verification->DRC->Errors->Load Errors , or click the corresponding button in the DRC tool bar. Load DRC errors form window will appear.

6) In the Checks section, select a listed item, and click the Load button. The corresponding error flag will be displayed in the design (see Figure 1 ).

To learn more about Guardian DRC, the different commands and their syntax as well as the different setup options, see the Guardian DRC user manual "guardian_users1.pdf" located in lib/expert/4.14.0.R/docs/ in your installation area.

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