// Gateway 2.12.10.R Verilog Netlist Generator
// Workspace name:       Q:\examples\gateway\web\design_examples\digital\003_one_bit_adder\one_bit_adder.workspace
// Simulation name:      Q:\examples\gateway\web\design_examples\digital\003_one_bit_adder\one_bit_adder.schlr
// Simulation timestamp: 20-Jul-2010 09:31:47

// Schematic name: one_bit_adder
module one_bit_adder(a, b, c_in, c_out, sum);
input a;
input b;
input c_in;
output c_out;
output sum;
wire a;
wire b;
wire c1;
wire c_in;
wire c_out;
wire s1;
wire s2;
wire sum;
xor21 I1 (.A(a), .B(b), .Y(s1));
and21 I2 (.A(a), .B(b), .Y(c1));
xor21 I3 (.A(s1), .B(c_in), .Y(sum));
and21 I4 (.A(s1), .B(c_in), .Y(s2));
or21 I5 (.A(s2), .B(c1), .Y(c_out));
endmodule

// End of the netlist

											

											// stimulus to test the 1-bit adder
module stimulus;
reg a, b, c_in;
wire sum, c_out;


//instantiate adder module
one_bit_adder X1(a, b, c_in, c_out, sum);


//apply stimulus
initial
begin
	//test all combinations
	a=1'b0; b=1'b0; c_in=1'b0;
	#5 a=1'b0; b=1'b0; c_in=1'b1;
	#5 a=1'b0; b=1'b1; c_in=1'b0;
	#5 a=1'b0; b=1'b1; c_in=1'b1;
	#5 a=1'b1; b=1'b0; c_in=1'b0;
	#5 a=1'b1; b=1'b0; c_in=1'b1;
	#5 a=1'b1; b=1'b1; c_in=1'b0;
	#5 a=1'b1; b=1'b1; c_in=1'b1;
	#5 $finish;
end

//results

initial
	$monitor($time, " sum = %b, a = %b, b=%b, c_in=%b", sum, a, b, c_in);

endmodule