005_clever : Using Clever tool to provide 3D view
Minimum Required Version: Expert 4.10.39.R, CLEVER 3.8.31.R
Expert allows CLEVER to be run directly from the currently-editing cell, or its clipped-out rectangular area. It uses an already-existing CLEVER input deck, and generates 3-D interconnect structure which can be displayed in TonyPlot3D.
Parasitic capacitances and resistances can also be calculated on the generated 3-D structure based on the 3-D field solver using CLEVER.
By adding appropriate commands in the input deck, CLEVER can generate electrodes from normal text objects put in the layout.
The actual operation steps are as follows:
- Start Expert and select File->Open to load the GDSII file integration_ex05.gds without a technology file. A dialog box will appear to inform you that no technology file is specified. Click OK to proceed the operation.
- Open the top cell INV_MET_POLY_COMB in Open Cell(s) dialog (see integration_ex05_1.png ).
- Select Tools->3-D Image->Setup to open the DeckBuild setup dialog (see integration_ex05_2.png ).
- Specify the CLEVER input deck integration_ex05.in in the Input file text field, and the CLEVER map file integration_ex05.map in the Map file text field. Also specify the output file integration_ex05.out, which does not exist before this example is run.
- Click OK to close the dialog.
- Select Tools->3-D Image->Cell . First, the DeckBuild window will appear, and CLEVER will run in it (see integration_ex05_3.png
).
As soon as CLEVER finishes the processing, TonyPlot3D will appear to show the generated 3-D structure (see integration_ex05_4.png ). - Select Tools->3-D Image->Clip-out and specify a rectangular area overlapping a part of the layout. CLEVER will be executed again for the specified area, and Tonyplot3D will show the resultant 3-D structure (see integration_ex05_5.png ).
Input Files
integration_ex05.in
go clever
Init GDS2="integration_ex05.gds" cell="INV_MET_POLY_COMB" layermap="integration_ex05.map" Depth=10 Silicon Map="integration_ex05.lmp" gasheight=100
Electrode Substrate
material silicon conductivity = 1000
##############################
# Define thickness variables #
##############################
set fieldoxide_thick=0.35 nominal
set poly1_thick=0.22
set ild_thick=0.75
set metal1_thick=0.62
set metal2_thick=0.62
set metal3_thick=0.62
set metal4_thick=0.62
set metal5_thick=0.99
set IMD1_thick=0.99
set IMD2_thick=0.99
set IMD3_thick=0.99
set IMD4_thick=0.99
set passiv_thick_ox=1.5
set passiv_thick_nit=1.2
##############################
# Define material variables #
##############################
# set Perm_Gateox=0.0001
set Perm_Gateox=3.9
set Perm_OXIDE=3.9
set Perm_PMD=4.2
set Perm_FOX=3.9
set Perm_TEOS=4.2
set Perm_HDP=4.1
set Perm_NIT=6
set poly_conduct=1.0/(6*$poly1_thick*1e-4)
set lil_conduct=1.0/(0.285*$poly1_thick*1e-4)
set Al_conduct_1=1.0/(70e-3*$metal1_thick*1e-4)
set Al_conduct_2=1.0/(70e-3*$metal2_thick*1e-4)
set Al_conduct_3=1.0/(70e-3*$metal3_thick*1e-4)
set Al_conduct_4=1.0/(70e-3*$metal4_thick*1e-4)
set Al_conduct_5=1.0/(45e-3*$metal5_thick*1e-4)
## Process Description ##
## Trench
Mask "AA"
Etch Silicon Thickness=$"fieldoxide_thick" Max
Strip Resist
Deposit Oxide Thickness=0.0 Max
## Gate oxide level
Deposit Material("Gateox") Thickness=0.01 Max
Mask "*GATE" reverse
Etch Material("Gateox")
Strip Resist
deposit oxide Thickness=0.0 Max
## Poly
Deposit material("poly") Thickness=$"poly1_thick" Max
Mask "CPOL"
Etch material("poly")
Strip Resist
Electrodes "*GATE" material("poly")
Electrodes "CPOL" material("poly")
## Contact
deposit material("PMD") thickness=$"poly1_thick" Min
deposit material("PMD") thickness=$"ild_thick" Max
Mask "CCON" Reverse
Etch material("PMD")
Etch oxide
Strip Resist
## Stop Source/Drain/Substrate Contacts Shorting to Substrate ##
## since substrate is treated as conductor here in other examples##
## substrate is a dielectric and thus no problem of short circuit ##
Deposit Material("Gateox") Thickness=0.01 Min
## Named polygons will be converted into electrodes ##
Electrodes "*CONT" Material("Gateox")
## Metal 1
deposit material("ALU1") thickness=$"metal1_thick" Max
Mask "CME1"
Etch material("ALU1")
Strip Resist
Electrodes "CME1" material("ALU1")
## passiv
deposit material("TEOS") thickness=$"passiv_thick_ox" Max
deposit material("NIT") thickness=$"passiv_thick_nit" Max
###############################
# Assign materials parameters #
###############################
material material("poly") conductivity=$poly_conduct
material material("ALU1") conductivity=$Al_conduct_1
material material("TEOS") permittivity=$Perm_TEOS
material material("PMD") permittivity=$Perm_PMD
material material("NIT") permittivity=$Perm_NIT
material Material("Gateox") permittivity=$Perm_Gateox
material material("ALU2") conductivity=$Al_conduct_2
material material("ALU3") conductivity=$Al_conduct_3
material material("HDP") permittivity=$Perm_HDP
## Save the 3D structure
save structure="integration_ex05.str"
## Parasitic Extraction ##
# Extract the resistance but keep only those above 1ohm
Interconnect Resistance AdaptR=0.10 MinRES=1 structure="res"
# First a calculation is made with 5% for every electrodes.
Interconnect Capacitance AdaptC=0.10 capsolver=1 structure="cap"
# Then Vdd since the precision asked is higher.
# Interconnect Capacitance contact="Vdd" adaptC=0.03 capsolver=1
# you can also precise all the electrodes with a precision from
# the lowest to the highest
# Interconnect Capacitance contact="Vdd" adapt=0.07 capsolver=1
# Interconnect Capacitance contact="Vss" adapt=0.05 capsolver=1
# Interconnect Capacitance contact="In" adapt=0.03 capsolver=1
# Interconnect Capacitance contact="Out" adapt=0.02 capsolver=1
Save Spice="integration_ex05.net"
tonyplot3d "integration_ex05.str"
quit
integration_ex05.lmp
; Define regions And CNPI CTOX NACTIVE And CPPI CTOX PACTIVE And NACTIVE CPOL NGATE And PACTIVE CPOL PGATE And NACTIVE !CPOL NSD1 And PACTIVE !CPOL PSD1 And NSD1 !CNWI NSD And PSD1 CNWI PSD Not !CNWI NSD NSUB Not CNWI PSD PSUB Not CCON CPOL SICONT ; Define mask for trench isolation Or NACTIVE PACTIVE AA ; Export new masks Export SICONT Export NSD Export NSUB Export PSD Export PSUB Export NACTIVE Export PACTIVE Export NGATE Export PGATE Export NSD1 Export PSD1 Export AA ; Define connectivity Connect CVIA CME2 Connect CME1 CVIA Connect CCON CME1 Connect CPOL CCON Connect NGATE CPOL Connect NSD CCON Connect PGATE CPOL Connect PSD CCON Connect NSUB SICONT Connect PSUB SICONT Connect CCON SICONT Attach LABEL CME1 Attach LABEL CPOL ; Define device name, gate, source/drain, substrate and connection ELEMENT MOS[myNMOS] NGATE NSD NSUB SICONT ELEMENT MOS[myPMOS] PGATE PSD PSUB SICONT
integration_ex05.map
CNWI drawing 1 0 CNWI res 1 3 CNWI nodrc 1 4 CTOX drawing 2 0 CTOX pin 2 1 CTOX res 2 3 CFLD drawing 4 0 CSTI drawing 5 0 CNOS drawing 6 0 CRES drawing 9 0 CCAP drawing 10 0 CPOL drawing 11 0 CPOL pin 11 1 CPOL res 11 3 CNPI drawing 12 0 COX3 drawing 13 0 CHVC drawing 24 0 CPPI drawing 14 0 CPO2 drawing 15 0 CCON drawing 16 0 CME1 drawing 17 0 CME1 pin 17 1 CME1 res 17 3 LABEL label 63 0
Graphics
These examples are for reference only. Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation
you should consider updating to a later version of the software.