Analog Custom Design Application Notes
Expert Layout
- Using Custom PCell Evaluators in Expert OA
- Efficient Bus Wiring in Expert
- Tips to Make PCells Using Javascript
- How to Modify MOSFET PCells for Expert’s Device Link
- Enabling Netlist Driven Layout with Standard Cells
- Creating LISA Scripts to Automate Layout Operations in Expert
- Customizing Expert with New Functions Using LISA
- Preserving Parametrized Cells When Translating Competitors’ Layout Database into Expert
DRC/LVS with SmartDRC/LVS and Calibre
- Expert’s Calibre RVE Interface for DRC/LVS
- Layout Verification in Batch Mode
- New Features Facilitate DRC Clean Layout and Parasitic Effect Debugging
- New Enhanced Possibilities of Netlist Comparison in Guardian LVS
- Using DRC Error Database to Analyze LVL Run Results
- A Suggested Approach for Layout Versus Schematic (LVS) Comparison Using Guardian LVS
- Logic Gate recognition in Guardian LVS
- Well Proximity and STI Stress Effect Parameters Extraction in SmartDRC/LVS
- Multi-Core Guardian DRC Benchmark Results
RC Extraction