SOI Technology
The full text most of these papers may be found at the IEEE website at www.ieee.org.
Ali A. Orouji, Hamid Amini Moghadam, A. Dideban,
“Double window partial SOI-LDMOSFET: A novel device for breakdown voltage improvement”,
Physica E: Low-dimensional Systems and Nanostructures, In Press, Accepted Manuscript, Available online 21 September 2010.
Michelly de Souza, Denis Flandre, Marcelo Antonio Pavanello,
“Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures”,
Cryogenics, Vol. 49, Issue 11, November 2009, pp. 599-604.
Rupendra Kumar Sharma, Ritesh Gupta, Mridula Gupta, R.S. Gupta,
“Dynamic performance of graded channel DG FD SOI n-MOSFETs for minimizing the gate misalignment effect”,
Microelectronics Reliability, Vol. 49, Issue 7, July 2009, pp. 699-706
N. A. B. A. Rahim, M. H. B. Abdullah, M. Rusop,
“Performance analysis of Si3N4 capping layer and SOI technology in sub 90 nm PMOS device”,
AIP Conference Proceedings, Vol. 1136, 2009, pp. 770-774
S. M. F. Bin Syed Adrus, M. H. Bin Abdullah, M. Rusop,
“Electrical analysis of 65 nm PMOS based on SOI technology”,
AIP Conference Proceedings, Vol. 1136, 2009, pp. 775-780
Michelly de Souza, Denis Flandre, Marcelo Antonio Pavanello,
“Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures Cryogenics”,
In Press, Corrected Proof, Available online 3 January 2009
D. Munteanu1, S. Cristoloveanu1 and E. Guichard2,
“3D Numerical Simulation of the Pseudo-MOS Transistor for SOI Film Characterization”
1LPCS/ENSERG, 23 rue des Martyrs BP 257, F-38016 Grenoble Cedex 1, France
2Silvaco Data System Sarl, 8, av. de Vignate 38610 Gières France
Maria Glória Caño de Andrade, João Antonio Martino,
“Threshold voltages of SOI MuGFETs”,
Solid-State Electronics, Vol. 52, Issue 12, December 2008, pp. 1877-1883
Michelly de Souza, Denis Flandre, Marcelo Antonio Pavanello,
“Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer”,
Solid-State Electronics, Vol. 52, Issue 12, December 2008, pp. 1933-1938
Chi-Woo Lee, Dimitri Lederer, Aryan Afzalian, Ran Yan, Nima Dehdashti, Weize Xiong, Jean-Pierre Colinge,
“Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs”,
Solid-State Electronics, Vol. 52, Issue 11, November 2008, pp. 1815-1820
Chung Ha Suh,
“A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET”,
Solid-State Electronics, Vol. 52, Issue 8, August 2008, pp. 1249-1255
Jean-Paul Mazellier, Olivier Faynot, Sorin Cristoloveanu, Simon Deleonibus, Philippe Bergonzo,
“Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis Diamond and Related Materials”,
Vol. 17, Issues 7-10, July-October 2008, pp. 1248-1251
H.P. Zhang, L. L. Sun, L. F. Jiang, L. Y. Xu, M. Lin,
“Process simulation of trench gate and plate and trench drain SOI nLDMOS with TCAD tools”,
Semiconductor Electronics, 2008. ICSE 2008.
IEEE International Conference on 25-27 Nov. 2008 pp. 92&95
K. Modzelewski, R. Chintala, H. Moolamalla, S. Parke, D. Hackler,
“Design of a 32 nm independently-double-gated FlexFET SOI transistor”,
2008 17th Biennial University/Government/Industry Micro/Nano Symposium, pp. 64-7, 2008
Chung Ha Suh,
“A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET”,
Solid-State Electronics, In Press, Corrected Proof, Available online 14 July 2008
Jean-Paul Mazellier, Olivier Faynot, Sorin Cristoloveanu, Simon Deleonibus, Philippe Bergonzo,
“Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis Diamond and Related Materials”,
In Press, Corrected Proof, Available online 3 April 2008
Tang Junxiong, Tang Minghua, Yang Feng, Zhang Junjie, Zhou Yichun, Zheng Xuejun,
“A temperature-dependent model for threshold voltage and potential distribution of fully depleted SOI MOSFETs”
Chinese Journal of Semiconductors, Vol 29, No. 1, Jan. 2008, pp. 45-49
A. Kranti et al.,
“How crucial is gate misalignment for low–Voltage operation in double gate SOI MOSFETs?”,
In Proc. Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EuroSOI 2008), Cork, Ireland, 2008
Rashmi et al.,
“Influence of gate–underlap design on the performance of 6T–SRAM cell with double gate SOI MOSFETs”,
In Proc. Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EuroSOI 2008), Cork, Ireland, 2008
B. Vincent, J. -F. Damlencourt, P. Rivallin, E. Nolot, C. Licitra, Y. Morand and L. Clavelier,
“Fabrication of SiGe-on-insulator substrates by a condensation technique: an experimental and modelling study”
30 January 2007 Semiconductor Science and Technology Vol. 22, Issue 3, art. no. 011, pp. 237-244
E. Simoen, C. Claeys, T.M. Chung, D. Flandre, M.A. Pavanello, J.A. Martino and J.-P. Raskin,
“The low-frequency noise behaviour of graded-channel SOI nMOSFETs”,
Solid-State Electronics, Vol. 51, Issue 2, February 2007, pp. 260-267
Feixia Yu and Ming-C. Cheng,
“Electrothermal simulation of SOI CMOS analog integrated circuits”,
Solid-State Electronics, Vol. 51, Issue 5, May 2007, pp. 691-702
Oana Moldovan, Antonio Cerdeira, David Jiménez, Jean-Pierre Raskin, Valeria Kilchytska, Denis Flandre, Nadine Collaert and Benjamin Iñiguez,
“Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications”,
Solid-State Electronics, Vol. 51, Issue 5, May 2007, pp. 655-661
Toru Tsuboyama, Yasuo Arai, Koichi Fukuda, Kazuhiko Hara, Hirokazu Hayashi, Masashi Hazumi, Jiro Ida, Hirokazu Ikeda, Yoichi Ikegami, Hirokazu Ishino, Takeo Kawasaki, Takashi Kohriki, Hirotaka Komatsubara, Elena Martin, Hideki Miyake, Ai Mochizuki, Morifumi Ohno, Yuuji Saegusa, Hiro Tajima, Osamu Tajima, et al.,
“R&D of a pixel sensor based on 0.15um fully depleted SOI technology”,
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Vol. 582, Issue 3, 1 December 2007, pp. 861-865
Tao Chuan Lim and G. Alastair Armstrong,
“Scaling issues for analogue circuits using Double Gate SOI transistors”,
Solid-State Electronics, Vol. 51, Issue 2, February 2007, pp. 320-327
Chung Tsung Ming, Raskin,
“DC AND AC ANALYSES OF NOVEL SOI MOSFET DEVICES USING 2D AND 3D NUMERICAL SIMULATIONS”
Jean-Pierre International Journal of Nanoscience. Vol. 5, No. 4-5, pp. 639-644. Aug. & Oct. 2006
A. Kranti et al.,
“DGSOI – from the OTA perspective”,
In Proc. Seventh European Workshop on Ultimate Integration of Silicon – ULIS 2006, Grenoble, France, pp. 53-54, 2006
Tsung Ming Chung, Jean-Pierre Raskin,
“DC AND AC Analyses of Novel SOI Mosfet Device Using 2D AND 3D Nunmerical Simulation”
International Journal of Nanoscience, Vol. 5, Nos. 4-5 (2006) 639-644
Gimenez, S. P., Ferreira, R. M. G., Martino, J. A.,
“Early Voltage behavior in circular gate SOI nMOSFET using 0.13 Î1⁄4m partially-depleted SOI CMOS technology”
2006 ECS Transactions 4 (1), pp. 309-318
Kranti, A., Armstrong, G. A.,
“Compact model for short channel effects in source/drain engineered nanoscale Double Gate (DG) SOI MOSFETs”
NSTI Nanotech 2006 Technical Proceedings 3, pp. 820-823
Joseph Ervin, Asha Balijepalli, Punarvasu Joshi, Vadim Kushner, Jinman Yang,
Trevor J. Thornton
“CMOS-Compatible SOI MESFETs With High Breakdown Voltage”
Electron Devices, IEEE Transactions on Vol. 53, Issue 12, Dec. 2006 pp. 3129-3135
A. Kranti et al.,
“Optimization of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFET with high gate dielectrics”,
Semiconductor Science and Technology, Vol. 21, no. 12, pp. 1563-1572, 2006
T.C. Lim et al.,
“Performance assessment of nanoscale multiple gate MOSFETs (MuGFETs) for rf applications”,
European Microwave Integrated Circuits (EuMIC) Conference 2006, Manchester, UK, pp. 308-311, 2006
A. Kranti et al.,
“Optimal design of source/drain extension (SDE) regions in multiple gate MOSFETs”,
In Proc. Seventh European Workshop on Ultimate Integration of Silicon – ULIS 2006, Grenoble, France, pp. 137-140, 2006
A. Kranti et al.,
“Modelling short channel effects in source/drain extension region engineered double gate MOSFETs”,
In Proc. Second Workshop of the Thematic Network on Silicon on Insulator Technology – EuroSOI 2006, Grenoble, France, pp. 131-132, 2006
M.S. Alam et al.,
“Analogue performance of double gate SOI transistors”,
International Journal of Electronics, Vol. 93, no. 1, pp. 1-18, 2006
T.C. Lim et al.,
“Parameter sensitivity for optimal design of 25nm double gate SOI transistors”,
Solid-State Electronics, Vol. 49, no. 6, pp, 1034-1043, 2005
T. C. Lim and G. A. Armstrong,
“Parameter sensitivity for optimal design of 65nm node double gate SOI transistors”
Solid-State Electronics, Vol. 49, Issue 6, June 2005, pp. 1034-1043
V. Kilchytska, D. Levacq, L. Vancaillie, D. Flandre,
“On the great potential of non-doped MOSFETs for analog applications in partially-depleted SOI CMOS process”
Solid-State Electronics, Vol. 49, Issue 5, May 2005, pp. 708-715
M. J. Lee, J. H. Cho, S. D. Lee, J. H. Ahn, J. W. Kim, S. W. Park, Y. J. Park, H. S. Min,
“Partial SOI type isolation for improvement of DRAM cell transistor characteristics”
IEEE Electron Device Letters, Vol. 26, Issue 5, May 2005, pp. 332-334
D. Lederer, J.-P. Raskin,
“Effective resistivity of fully-processed SOI substrates”
Solid-State Electronics, Vol. 49, Issue 3, March 2005, pp. 491-496
M. Wiatr, P. Seegebrecht,
“Impact of floating silicon film on small-signal parameters of fully depleted SOI-MOSFETs biased into accumulation”
Solid-State Electronics, Vol. 49, Issue 5, May 2005, pp. 779-789
K. Nishiguchi, H. Inokawa, Y. Ono, A. Fujiwara, Y. Takahashi,
“Multifunctional Boolean logic using single-electron transistors”
IEICE Transactions on Electronics, Vol. E87-C, Issue 11, November 2004, pp. 1809-1817
B. Ashcroft, B. Takulapalli, J. Yang, G. M. Laws, H. Q. Zhang, N. J. Tao, S. Lindsay, D. Gust, T. J. Thornton,
“Calibration of a pH sensitive buried channel silicon-on-insulator MOSFET for sensor applications”,
Physica Status Solidi (b), Vol. 241, Issue 10, Aug. 2004, pp. 2291-2296
N. V. T. D’Halleweyn, J. Benson, W. Redman-White, K. Mistry, M. Swanenberg,
“MOOSE: A physically based compact DC model of SOI LDMOSFETs for analogue circuit simulation”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 10, October 2004, pp. 1399-1410
S. Mitra, A. Salman, D. P. Ioannou, C. Tretz, D. E. Ioannou,
“Double gate (DG)-SOI ratioed logic with symmetric DG load&A novel approach for sub 50 nm low-Voltage/low-power circuit design”
Solid-State Electronics, Vol. 48, Issue 10-11 SPEC. ISS., October 2004, pp. 1727-1732
F. Yu and M. -C. Cheng,
“Application of heat flow models to SOI current mirrors”
Solid-State Electronics, Vol. 48, Issue 10-11 SPEC. ISS., October 2004, pp. 1733-1739
J. Lin, M. Shen, M. -C. Cheng, M. L. Glasser,
“Efficient thermal modeling of SOI MOSFETs for fast dynamic operation”
IEEE Transactions on Electron Devices, Vol. 51, Issue 10, October 2004, pp. 1659-1666
B. Ashcroft, B. Takulapalli, J. Yang, G. M. Laws, H. Q. Zhang, N. J. Tao, S. Lindsay, D. Gust, T. J. Thornton,
“Calibration of a pH sensitive buried channel silicon-on-insulator MOSFET for sensor applications”
Physica Status Solidi (B) Basic Research, Vol. 241, Issue 10, August 2004, pp. 2291-2296
S. S. Suryagandh, M. Garg, J. C. S. Woo,
“A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs”
IEEE Transactions on Electron Devices, Vol. 51, Issue 7, July 2004, pp. 1122-1128
A. Kranti, T. M. Chung, D. Flandre, J. -P Raskin,
“Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications”
Solid-State Electronics, Vol. 48, Issue 6, June 2004, pp. 947-959
C. E. Png, S. P. Chan, S. T. Lim, et al.,
“Optical phase modulators for MHz and GHz modulation in silicon-on-insulator (SOI)”
Journal Of Lightwave Technology, Vol. 22, No. 6, June 2004, pp. 1573-1582
Ching Eng Png, Seong Phun Chan, Soon Thor Lim, G. T. Reed,
“Optical phase modulators for MHz and GHz modulation in silicon-on-insulator (SOI)”
Journal of Lightwave Technology, Vol. 22, No. 6, June 2004, pp. 1573-82
M. C. Cheng, F. Yu, L. Jun, M. Shen and G. Ahmadi,
“Steady-state and dynamic thermal models for heat flow analysis of silicon-on-insulator MOSFETs”
Microelectron. Reliab., Vol. 44, Mar 2004, pp. 381-396
M. C. Cheng, F. Yu, P. Habitz and G. Ahmadi,
“Analytical heat flow modeling of silicon-on-insulator devices”
Solid-State Electronics, Vol. 48, Mar 2004, pp. 415-426
P. Pandey, B. B. Pal and S. Jit,
“A new 2-D model for the potential distribution and threshold Voltage of fully depleted short-channel Si-SOI MESFETs”
IEEE Trans. Electron Devices, Vol. 51, Feb 2004, pp. 246-254
C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, S. Deleonibus,
“Lateral interband tunneling transistor in silicon-on-insulator”
Applied Physics Letters, Vol. 84, Issue 10, 8 March 2004, pp. 1780-1782
F. Allibert, J. Pretet, G. Pananakakis, S. Cristoloveanu,
“Transition from partial to full depletion in silicon-on-insulator transistors: Impact of channel length”
Applied Physics Letters, Vol. 84, Issue 7, February 2004, pp. 1192-1194
W. -S. Son, S. -G. Kim, Y. -H. Sohn, S. -Y. Choi,
“A new SOI LDMOSFET structure with a trench in the drift region for a PDP scan driver IC”
ETRI Journal, Vol. 26, Issue 1, February 2004, pp. 7-12
F. Yu, M. -C. Cheng, P. Habitz, G. Ahmadi,
“Modeling of thermal behavior in SOI structures”
IEEE Transactions on Electron Devices, Vol. 51, Issue 1, January 2004, pp. 83-91
G. T. Reed, G. Z. Masanovic, W. R. Headley, C. E. Png, S. P. Chan, S. T. Lim, V. M. N. Passaro, D. Hak, O. Cohen, M. Paniccia,
“Small devices in SOI: Fabrication and design issues”
Proceedings of SPIE&The International Society for Optical Engineering, Vol. 5357, 2004, pp. 75-86
C. E. Png, G. T. Reed, W. R. Headley, K. P. Homewood, A. Liu, M. Paniccia, R. M. H. Atta, G. Ensell, A. G. R. Evans, D. Hak, O. Cohen,
“Design and experimental results of small silicon-based optical modulators”
Proceedings of SPIE&The International Society for Optical Engineering, Vol. 5356, 2004, pp. 44-55
I. Ionica, L. Montès, S. Ferraton, J. Zimmermann, V. Bouchiat, L. Saminadayar,
“Silicon nanostructures patterned on SOI by AFM lithography”
2004 NSTI Nanotechnology Conference and Trade Show&NSTI Nanotech 2004, Vol. 3, 2004, pp. 165-168
A. M. Ionescu, D. Munteanu, N. Hefyene, C. Anghel,
“Compact modeling of weak inversion generation transients in SOI MOSFETs”
Journal of the Electrochemical Society, Vol. 151, Issue 6, 2004
C. E. Png, G. T. Reed, R. M. H. Atta, G. Ensell, A. G. R. Evans,
“Development of small silicon modulators in Silicon-On-Insulator (SOI)”
Proceedings of SPIE&The International Society for Optical Engineering, Vol. 4997, 2003, pp. 190-197
S. Mitra, A. Salman, D. P. Ioannou, C. Tretz and D. E. Ioannou,
“Low Voltage/low power sub 50 nm double gate SOI ratioed logic”
IEEE International SOI Conference 2003, 29 Sep&2 Oct 2003, pp. 177-178
S. S. Suryagandh, M. Garg and J. C. S. Woo,
“A detailed analysis of SOI MOSFETs for SOC design”
IEEE International SOI Conference 2003, 29 Sep&2 Oct 2003, pp. 147-148
M Jagadesh Kumar and Vinod Parihar,
“A Novel High Current Gain Lateral PNP Transistor on SOI for Complimentary Bipolar Technology”
Proc. of 2003 International Semiconductor Device Research Symposium, Washington DC, December 10-12 2003, ppg 268-269
Feixia Yu and Ming-C Cheng,
“Heat Flow in SOI Current Mirrors”
Proc. of 2003 International Semiconductor Device Research Symposium, Washington DC, December 10-12 2003, pp. 392-393
A. Raman, D. G. Walker, T. S. Fisher,
“Simulation of nonequilibrium thermal effects in power LDMOS transistors”
Solid-State Electronics, Vol. 47, Issue 8, August 2003, pp. 1265-1273
R. J. Luyken, T. Schulz, J. Hartwich, L. Dreeskornfeld, M. Stadele, W. Rosner,
“Design considerations for fully depleted SOI transistors in the 25-50 nm gate length regime”
Solid-State Electronics, Vol. 47, July 2003, pp. 1199-1203
M. Jagadesh Kumar and C. Linga Reddy,
“2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI”,
Microelectronics Reliability, Vol. 43, Issue 7, July 2003, pp. 1145-1149
M. Kittler, R. Granzner, F. Schwierz, W. Henschel, T. Wahlbrink, H. Kurz,
“Simulation and optimization of EJ-MOSFETs”
Solid-State Electronics, Vol. 47, July 2003, pp. 1193-1198
Xiangli Li, S. A. Parke and B. M. Wilamowski,
“Threshold Voltage control for deep sub-micrometer fully depleted SOI MOSFET”
Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium 2003, 30
T. H. Tan and A. K. Goel,
“Zero-temperature-coefficient biasing point of a fully-depleted SOI MOSFET”
Microwave and Optical Technology Letters, Vol. 37, Jun. 2003, pp. 366 370
M.-C. Cheng, R. Wettimuny, P. Habitz, G. Ahmadi,
“Thermal simulation for SOI devices using thermal-circuit models and device simulation”
Solid-State Electronics, Vol. 47, February 2003, pp. 345-351
Niraj Subba, Souvick Mitra, Akram Salman and Dimitris E. Ioannou,
“Device physics considerations for SOI domino circuit design”
Solid-State Electronics, Vol. 47, Issue 2, Feb. 2003, pp. 175-179
S. Mitra, A. Salman, D. P. Ioannou, C. Tretz, D. E. Ioannou,
“Low Voltage / Low Power sub 50 nm Double Gate SOI Ratioed Logic”
IEEE International SOI Conference, 2003, pp. 177-178
S. Mitra, A. Salman, D. P. Ioannou, C. Tretz, D. E. Ioannou,
“DG-SOI ratioed logic with symmetric DG load&a novel approach for sub 50 nm LV/LP circuit design”
2003 International Semiconductor Device Research Symposium (IEEE Cat. No.03EX741), 2003, pp. 390
D. Munteanu, G. Le Carval, C. Fenouillet-Béranger, O. Faynot,
“Investigation of nonstationary transport and quantum effects in realistic deep submicrometer partially depleted SOI technology”
Electrochemical and Solid-State Letters, Vol. 5, Issue 5, May 2002
Jong-Tae Park and Jean-Pierre Colinge,
“Multiple-Gate SOI MOSFETs: Device Design Guidelines”
IEEE Trans. Elect. Devices, Vol. 49, Issue 12, Dec. 2002, pp. 2222-2229
S. Adriaensen and D. Flandre,
“Analysis of the thin-film SOI lateral bipolar transistor and optimization of its output characteristics for high-temperature applications”
Solid-State Electronics, Vol. 46, Issue 9, Sep. 2002, pp. 1339-1343
J. Yang, T. J. Thornton, M. Kozicki, L. de la Garza and D. Gust,
“Molecular control of the threshold Voltage of an NMOS inversion layer”
Microelectronic Engineering, Vol. 63, Issues 1-3, Aug. 2002, pp. 135-139
M. Dehan and J. -P. Raskin,
“An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics”
Solid-State Electronics, Vol. 46, July 2002, pp. 1005-1011
M. Jagadesh Kumar and D. Venkatesh Rao,
“A new lateral PNM Schottky collector bipolar transistor (SCBT) on SOI for nonsaturating VLSI logic design”
IEEE Trans. Electron Devices, Vol. 49, Jun. 2002, pp. 1070-1072
C. Ravariu, A. Rusu, F. Ravariu, D. Dobrescu and L. Dobrescu,
“From -MOSFET with silicon on oxide to -MOSFET with silicon carbide on nitride”
Diamond and Related Materials, Vol. 11, Issues 3-6, Mar.-Jun. 2002, pp. 1268-1271
J. Yang, T. J. Thornton, S. M. Goodnick, M. Kozicki and J. Lyding,
“Buried channel silicon-on-insulator MOSFETs for hot-electron spectroscopy”
Physica B: Condensed Matter, Vol. 314, March 2002, pp. 354-357
S. Mitra, A. Salman, D. P. Ioannou, D. E. Ioannou,
“LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load”
IEEE International SOI Conference, 2002, pp. 66-67
S. Adriaensen, V. Dessard, D. Flandre,
“A Voltage reference compatible with standard SOI CMOS processes and consuming 1pA to 50nA from room temperature up to 300”
IEEE International SOI Conference, 2002, pp. 130-131
Jong-Jun Kim, Hwan-Sool Oh, Doo-Yeon Chung, and Jong-Ho Lee,
“Implementation of specific frequency response using SOI photodetector cell”
Journal of the Korean Physical Society, Vol. 40, No. 1, January 2002, pp. 34-38
A. Cerdeira, M. Estrada, R. Quintero, D. Flandre, A. Ortiz-Conde and F. J. García Sánchez,
“New method for determination of harmonic distortion in SOI FD transistors”
Solid-State Electronics, Vol. 46, Issue 1, Jan. 2002, pp. 103-108
J. Pretet, D. Ioannou, N. Subba, S. Cristoloveanu, W. Maszara and C. Raynaud,
“Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs”
Solid-State Electronics, Vol. 46, Issue 11, 2002, pp. 1699-1707
D. Tomaszewski, L. Lukasiak, J. Gibki, K. Doman´ski, A. Jakubowski, A. Zarba,
“Measurement and modelling of SOI MOSFETs capacitances”
Proceedings of SPIE&The International Society for Optical Engineering, Vol. 4746 I, 2002
Jörgen Olsson,
“Self-heating effects in SOI bipolar transistors”
Microelectronic Engineering, Vol. 56, Issues 3-4, August 2001, pp. 339-352
E. Rauly, B. Iñiguez, D. Flandre,
“Investigation of deep submicron single and double gate SOI MOSFETs in accumulation mode for enhanced performance”
Electrochemical and Solid-State Letters, Vol. 4, Issue 3, March 2001
O. Faynot, T. Poiroux and J. L. Pelloie,
“Compact analytical modeling of SOI partially depleted MOSFETs with LETISOI”
Solid-State Electronics, Vol. 45, Issue 4, April 2001, pp. 599-605
Mikael Johansson, Jonas Berg and Stefan Bengtsson,
“High frequency properties of silicon-on-insulator and novel depleted silicon materials”
Solid-State Electronics, Vol. 45, Issue 4, April 2001, pp. 567-573
P. D. Hewitt and G. T. Reed,
“Improved modulation performance of a silicon p-i-n device by trench isolation”
Journal of Lightwave Technology, Vol. 19, Issue 3, March 2001, pp. 387-390
J. Pretet, N. Subba, D. Ioannou, S. Cristoloveanu, W. Maszara, C. Raynaud,
“Explaining the reduced floating body effects in narrow channel SOI MOSFETs”
IEEE International SOI Conference, 2001, pp. 25-26
S. Jit, P. Pandey, A. Kumar, S. K. Gupta,
“Modified boundary condition at Si-SiO2 interface for modeling of threshold Voltage and subthreshold swing of short-channel SOI MESFET´s”
Solid-State Electronics, Vol. 49, Issue 1, January 2005, pp. 141-143
F. Yu, M. -C. Cheng,
“Thermal modeling of silicon-on-insulator current mirrors”
Proc.&IEEE International SOI Conference, 2004, pp. 81-83
Widiez J., Daug F., Vinet M., Poiroux T., Previtali B., Mouis M., Deleonibus S.,
“Experimental gate misalignment analysis on double gate SOI MOSFETs”
Proc.&IEEE International SOI Conference, 2004, pp. 185-186
J. Lolivier, J. Widiez, M. Vinet, T. Poiroux, F. Daug, B. Previtali, M. Mouis, J. Jommah, F. Balestra, S. Deleonibus,
“Experimental comparison between Double Gate, Ground Plane, and Single Gate SOI CMOSFETs”
ESSCIRC 2004&Proceedings of the 34th European Solid-State Device Research Conference, 2004, pp. 77-80
J. Lolivier, M. Vinet, T. Poiroux, B. Previtali, T. CheVolleau, J. M. Hartmann, A. -M. Papon, R. Truche, O. Faynot, F. Balestra, S. Deleonibus,
“10nm-gate-Iength transistors on ultra-thin SOI film : Process realization and design optimisation”
Proceedings&IEEE International SOI Conference, 2004, pp. 17-18
T. C. Lim, N. D. Jankovic, G. A. Armstrong,
“Scaling of fully depleted SOI mosfets with P+poly sige gates”
10th International Symposium on Integrated Circuits, Devices and Systems, ISIC-2004: Integrated Sys pp. 20-21
C. D. G. Dos Santos, M. A. Pavanello, J. A. Martino, D. Flandre, J. P. Raskin,
“Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures”
Electrochemical Society Proceedings, Vol. 3, 2004, pp. 9-14
T. Hoang, P. LeMinh, J. Holleman, V. Zieren, M. J. Goossens, J. Schmitz,
“A high efficiency lateral light emitting device on SOI”
The 12th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, EDMO, 8-9 November 2004
H. W. Kim, S. C. Kim, K. S. Seo, W. Bahng, E. D. Kim,
“Device characteristics of the SOI LIGBT with dual-epi layers”
Proc.&IPEMC 2004: 4th International Power Electronics and Motion Control Conference
Ravariu C. Ravariu F. Rusu A. Dobrescu D. Dobrescu L.,
“The Modeling of a SOI Microelectromechanical Sensor”
Proc. SISPAD 2001, pp. 328-331
Park J-K., Deshpande H.V., Woo J.C.S.,
“The Effect of Impact Ionization on the subthreshold Leakage Current in N-Channel Double-Gated SOI Transistors”
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