The full text for most of these papers may be found at the IEEE website at www.ieee.org.
Keh-Jeng Chang, Jyh-Jeng Chou, Hung-Chih Li, and Kuo-Cheng Chang,
“Impact quantification of the dummy metal fills on nanometer VLSI designs for DFM”,
International Symposium on VLSI Design, Automation and Test, 2008. VLSI- DAT 2008. IEEE, April 2008, pp. 291 – 294.
C. Xu, R. Gharpurey, T. S. Fiez, K. Mayaram,
“A green function-based parasitic extraction method for inhomogeneous substrate layers”
Proceedings – Design Automation Conference, 2005, pp. 141-146.
A.K. Goel, and H. Gopinathannair,
“Capacitance extraction for the nanoscale on-chip interconnects”
IEEE International Conference on Semiconductor Electronics, Dec 2004, pp. 112- 116.
C. Renard (SILVACO Data Systems), P. Scheiblin, F. De Crecy, A. Ferron, E. Guichard, P. Holliger, C. Laviron,
“Methodology for prediction of ultra shallow junction resistivities considering uncertainties with a genetic algorithm optimization”
2004 NSTI Nanotechnology Conference and Trade Show – NSTI Nanotech 2004, Vol. 2, 2004 NSTI Nanote.
D. Lederer, J. -P. Raskin,
“Substrate loss mechanisms for microstrip and CPW transmission lines on lossy silicon wafers”
Solid-State Electronics, Vol. 47, November 2003, pp. 1927-1936.
Sheehan DP, Putnam AR, Wright JH,
“A solid-state Maxwell demon”
Foundations of Physics, 32 (10): 1557-1595 OCT 2002.
V. Narayanan, Z. Liu, Y. -M. N. Shen, M. Kim, E. C. Kan,
“Reduction of metal-semiconductor contact resistance by embedded nanocrystals”
Technical Digest – International Electron Devices Meeting, 2000, pp. 87-89.
B. Froment, E. Guichard, B. Borot, S. Hanriat, J. Cluzel, J.-P.
Schoellkopf, and H. Jaouen,
“New interconnect capacitance characterization method for multilevel metal CMOS processes”
IEEE International Conference on Interconnect Technology, 1999, pp. 224 – 226.
S. Putot, F. Charlet, and P. Witomski,
“A fast and accurate computation of interconnect capacitance”
International Electron Device Meeting, Dec. 1999, pp. 893-896.
D. Salameh and D. Linton,
“Study of the effect of various parameters on nonlinear transmission-line (NLTL) performance”
IEEE Transactions on Microwave Theory and Techniques, Vol. 47, Issue 3, March 1999, pp. 350 -353.
Salamh, D. and Linton, D.,
“Nonlinear transmission line (NLTL) design as a pulse generator”
IEEE High Frequency Postgraduate Student Colloquium, 1996, pp. 7-10.
Tan, Jilin and Pan, Guang-Wen,
“Full wave analysis of transmission lines in a multilayer substrate with heavy dielectric losses”
IEEE Transactions on Components, Packaging & Manufacturing Technology, Part B, August 1996, Vol. 19 Issue 3. pp. 621-627.