A. Previous articles in the Simulation Standard have highlighted the diffusion models required for accurate simulation of shallow source/drain junction formation[1] and Reverse Short Channel Effect (RSCE)[2][3]. However for complete simulation of MOS short channel behavior it is necessary to consider the diffusion of the channel implants before the source/drain processing.
Q: I want to draw several long wires, with precise positioning of both ends. I am used to doing this as follows:
Maverick is a sophisticated full chip hierarchical netlist extractor [1]. It augments the existing CELEBRITY framework which includes state-of-the-art software for VLSI layout editing, hierarchical design rule checking and layout versus schematic comparison. The latest release of Maverick is equipped with many new interface features, including the ability to search for a net by name, and new engine upgrades, such as extraction of parameters of active devices. A new numerical procedure has been developed for resistance extraction of complex geometrical shapes.
In a previous issue of Simulation Standard for Process and Device Engineers[1] the simulation of a three stage CMOS ring oscillator using ATLAS/MixedMode was introduced. The MOSFETs used in the MixedMode simulation were created using analytical doping profiles specified within ATLAS. This article is intended to investigate some of the effects of process variation on ring oscillator performance. Thus, the individual devices in the ring oscillator circuit are created usingthe two-dimensional process simulation program, ATHENA.
There has been a significant increase in the popularity of liquid crystal displays with control circuitry being placed on to the glass (system on a panel). This has been made possible by the technological improvements of thin-film-transistors (TFTs) manufactured on glass substrates. The sudden popularity is a result of the move away from the traditional use of amorphous silicon towards polycrystalline silicon. The increase in performance by this switch has allowed these TFTs to be applied to applications beyond pixel control transistors.
ATHENA version 5.0 includes a new Binary Collision Algorithm (BCA) for accurate Monte-Carlo implant modeling down to sub-1keV energies. This new BCA code is a 3D model that takes account of channeling in all possible crystal directions, not just the vertical direction. Accurate modeling of all channeling directions becomes an important factor for low energy implants such as is used by the new generation of very deep submicron devices.
A. The BSIM3_MG routine in SOI module of UTMOST III can be used to extract SOI model parameters. The SOI BSIM3_MG routine operation is similar to the one in MOS module. However the “Measurement Variables” (Figure 1) and biasing of the SOI device is unique.
The addition of important features in the latest version of SPAYN (1.7.3.R) makes it an even more useful and versatile statistical parameter and yield analysis tool. The list of spice models available in SPAYN has been expanded to include the EKV MOSFET model. The new “Golden Device” function locates the observation in a particular database that is closest to the theoretical mean observation. This “Golden Device” is then considered to be the average observation that best characterizes that database. Several new plotting symbols have been added to the scattergram plotting facility allowing a clearer graphical representation of data. It is also now possible to locate the position of the minimum or maximum record in a given database without the need to manually sort through the complete data set.
Users of the Cadence Design Framework II (DFII, versions 4.4.0 and above) have been enjoying a tight integration between SmartSpice and the Analog Artist Electrical Design System and Composer Design Entry tools. This integration is achieved via the Cadence Spice Socket (cdsSpice) and the Open Analog Simulation Integration Socket (OASIS). It has been comprehensively documented in previous issues of the Simulation Standard, and also in a new application note (Ref No. SS/99-2).
The intrinsic capacitance parameter extraction routine (INTCAP) is in the CAP analysis section of the UTMOST III MOS module (Routine#67). The INTCAP routine has 5 different intrinsic cap measurements and a “simulation only” capability for all intrinsic caps. Recent developments have improved the INTCAP routine. Users should have UTMOST III MOS module version 15.2.0 or higher to be able use the examples and explanations presented in this article. The INTCAP routine allows users to measure the MOS capacitances when the device is under DC bias and conducting current.