A new feature has been added to Silvaco’s device simulator ATLAS, which allows the simulation of ohmic heating effects in metals using the Giga or Giga3D modules. The feature has been included in response to metal heating problems that increasingly occur in interconnects for very aggressive technologies.
Impact ionization plays an important role in the design of many semiconductor devices. Since impact ionization is both temperature and electric field dependent, it is important to use a model which has the correct functional behavior. For most devices impact ionization defines the safe region of operation within a moderate range of temperatures, so the temperature dependence of impact ionization is of lessor importance than the field dependence. However, for devices which must operate outside of the usual temperature limits, or which carry enough current to heat themselves out of those limits, both field dependence and temperature dependence of the model must be accurate.
ATLAS may be used to study these effects. A standard experiment for studying recombination in silicon is the transient decay of photoexcited carriers – known as the Stephenson-Keyes method for measuring minority carrier lifetime [1]. This method has been well described in [2]. The following is a description of the implementation of this experiment using the 2D device simulator ATLAS.
BSIM3SOI version 3.0 model was released on May 2002 by UC Berkeley. This model includes both Partially and Fully depleted models. This model is now implemented in SmartSpice and can be selected according to LEVEL selector.
HiSIM is based on a charge-sheet model. IDS current is described using only one equation, and there-fore is continuous over the whole range of operating regions. This improves MOSFETs modeling regarding at least two points. Equations are continuous over all operation regions, as well as their derivatives. This is a key point for today’s analog circuits, where performance is very much dependent on high order derivatives. Parameter number is dramatically reduced (by a factor 5) for the same level of accuracy. Parameters are not interdependent anymore, making extraction easier. Furthermore, a set of parameters is valid for all channel lengths.
HiSIM is a MOSFET model for SPICE circuit simulation that has been developed by Hiroshima University and STARC Company. This model present several advantage on the extraction point of view, with a reasonable number of parameters, a physical reliability of the equations for a wide range of geometries (down to 0.1um) and a unified description of devices characteristics for all bias conditions. It has been implemented in Silvaco Spice Simulator, SmartSpice and in our current extraction software UTMOST III.
The input impedence of most network analyzers are around 1 MOhm, which is relatively small. Due to this low impedence the leakage current on the Base port (Typically Port1) becames high and makes it impossible to find the correct collector current bias when “Linear IC” or “Log IC” measurement modes are selected in FT_CE routine.
A new version of Savage DRC system taps the full power of multiprocessor computers by introducing simultaneous execution of DRC commands from a DRC deck. A DRC deck is a set of DRC rules to be performed for a given layout. For typical DRC decks, the described approach alone delivers high processor utilization and speed-up. Further improvements are possible using parallelization by decomposition of IC layout data and exploiting its hierarchy.
Silvaco Data Systems announces the release of CELEBRITY CAD suite: Expert layout editor, Savage DRC system and Guardian LVS for Linux platform.
It is well-known that parasitic effects are no longer negligible for modern integrated circuit technology. Among the most important parasitic effects limiting the chip performance are interconnect related problems like extensive signal delays and crosstalk. The main numeric problem is extraction of parasitic capacitance, because it is a more complicated task than resistance extraction. The latest codes use directly 3D electrostatic solvers for this purpose. But the disadvantage of such approach is prohibitively long solution time for the problem. So the simplest model of 3D structures, when layout is splitted to 2D small pieces, can be used when it is necessary to handle complete IC’s in a reasonable amount of time.