BSIM4 Model Verilog-A Implementation
The Verilog-A hardware description language opens many areas to SPICE users in the field of compact models, allowing manufacturers and universities to study or customize the existing models.
Entries by Erick Castellon
Stress Effect Model in BSIM3v3 Model
Stress effect models are now implemented in major models such as BSIM4 or HiSIM. The need for evermore accurate models with a strong relation to technology is accute. Since BSIM3v3 is still a widely-used model and has not been totally replaced by its successor, an improvement was made to the model in SmartSpice to fulfill customers need for stress effect equations.
New Philips MOS20 LDMOS Model in SmartSpice
Philips MOS20 was released in January 2004. Its purpose is to provide a high-voltage compact model to describe both operation of the channel region and drift region under the thin gate oxide.
Sometimes I have problem to skip cells when importing cells
Q: Sometimes I have problem to skip cells when importing cells with the same names from reference library. Once we skip one cell, expert will complain other cells already exist in the new library.
A: To process name collisions for several cells when you try to skip some of them:
1. click ‘All Existing’ button in Cell Name Collision dialog. The name of all existing cells become highlighted in grey.
Guardian DRC vs. Other DRC Systems, I
1. Introduction
This article begins a series of articles that describe the compatibility of Guardian DRC system[1] in terms of functionality: command set, syntax and implementation with other leading industrial DRC systems. The purpose of this series is to facilitate the usage of Guardian DRC system by the designers who are already familiar with some other DRC systems.
Schematic Driven Layout
Expert schematic driven layout (SDL) is a CAD tool which increases the productivity of layout design by automating cell generation and providing visual cues to assist the wiring process. In the current implementation, schematic driven layout is used to automatically create IC layouts based on information from a netlist. Cell instances are created from existing cells.
Interactive P-cell Generation
1. Abstract
Parameterized cells (P-cells) significantly increase the productivity of layout designers. Silvaco International’s tool Expert has been designed to aid layout designers through its ability to support and manipulate P-cells based on its LISA script language. This simulation standard will demonstrate the capability of Expert and will identify its inherent benefits to the layout engineer.
Interconnect Parasitic Accuracy & Speed Improvements in New CLEVER Release
Introduction
This article introduces the new features and numerical schema implemented in the most recent release of Clever from Silvaco. In this new release, both memory handling and simulation time are optimized to allow the input of larger simulation structures. In addition, the release offers greater control over the accuracy benchmarks necessary for extracted parasitic elements.
Is there a way to automatically specify mesh spacing in ATHENA?
Q. Is there a way to automatically specify mesh spacing in ATHENA?
A. Yes, there are three ways to automatically specify grid spacing. The most preferred method is described below and could best be described as “semi-automatic”. The other methods not described below utilize the MaskViews/ATHENA interface and the adaptive meshing feature respectively.
Topography Simulation of Trench Etch Using Monte Carlo Plasma Etch Model with Polymer Re-deposition
1. Introduction
The topography simulation module, Elite has constantly been improved in order to simulate advanced processes, which are becoming more complex with device miniaturization and further integration of VLSI circuits. Elite is a two dimensional topography simulation module that works within ATHENA, and includes the etching and deposition models neccessary to simulate diverse modern technologies.