Variation aware design for advanced nodes and low power technologies
Designers’ characterization and verification tasks have become more critical due to scaled down process technologies such as FinFET or FDSOI, and the drive towards lower Vdd/Vth processes. As a result, massive usage of Monte Carlo simulations has become a common practice to ensure robust designs that meet yield requirements. Though brute force Monte Carlo is accurate it is impractical in terms of time and simulation licenses consumed. More efficient techniques are needed for practical variation aware design.
Silvaco’s VarMan delivers innovative Monte Carlo techniques that allow for fast examination of analog cells or AMS/RF IC’s, and enables robust high-sigma investigation of highly replicated design elements such as memory bitcells or logic standard cells.VarMan’s innovative sampling techniques will help designers address variation issues much faster and at a lower cost.
What attendees will learn:
- Design challenges to account for variation
- Monte Carlo in practice, how to be efficient and minimize risks
- Variation aware design for analog
- Variation aware design for memory and standard cells