Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
One commonality across semiconductor market segments is the need for memory. However, memory characteristics and interfaces vary greatly depending on the market segment and application. This webinar will focus on a specific class of memory devices – targeted to mobile and IoT applications – that use “SPI” (Serial Peripheral Interface) signaling.
SPI was developed by Motorola in 1979 for short-distance communication within embedded systems. Its popularity grew quickly, and SPI soon spawned many variants but lacked a unifying standard. Almost 30 years after its inception, SPI was adopted by FLASH memory manufacturers to satisfy growing demand in the emerging IoT space. As edge devices became more complex, a push for greater memory performance resulted, and the SPI interface evolved to meet these new challenges: Dual, Quad, Octal and Octal DDR (Double Data Rate) SPI variants ensued. With Octal DDR, the performance of the interface was sufficient to support RAM devices in addition to FLASH devices, some much-needed standardization was realized in the form of several similar, overlapping specifications.
Today’s IoT systems need a solution for interfacing with these memories: the Octal SPI Memory Controller. This product from Silvaco contains powerful features such as XIP (Execute In Place) and supports FLASH and PSRAM memories.
What You Will Learn
- Octal SPI Controller architecture and key features
- Implementation of a typical Octal SPI integration in an embedded system
- Operating modes will be defined and explained
- Seamless memory access, support for a range of memory devices, and flexibility to accommodate various clocking and integration scenarios
- XIP (Execute in Place) and PSRAM support