Hierarchical Layout versus Schematic

1. Introduction

A new Hierarchical Layout versus Schematic (HLVS) system that provides significant improvement in verification of huge circuits is described. Other of LVS verification tools perform a netlist flattening and comparison in transistor level [1, 2]. These tools are based on standard graph isomorphism algorithms and are sufficiently efficient in practice. Their running time is almost linear in the size of compared devices: O (N_m), where N is the number of compared devices and m is value a little larger than 1. These tools are not effective enough to verify circuits containing tens of millions of transistors. There is a need for hierarchical comparison of two netlists. This proposed hierarchical approach does not flatten the netlist. The comparison is carried out for separate cells. Once a cell is checked, its contents are not used later in comparison, only the verification of connectivity to ports of this cell is performed. This approach enables a large decrease in the number of compared elements and, consequently, the run time of HLVS verification.

2. Some Features of Guardian HLVS

Compared netlists should satisfy to some conditions to make hierarchical verification more effective:

• Both compared netlists should have hierarchical structure. Otherwise, if at least one netlist is flat, you will not obtain the advantages of hierarchical approach of LVS verification. Notice, exactly the same hierarchical structure of netlists is not required. The netlists can have different number of cells and levels of hierarchy
• Guardian HLVS can handle different number of ports of equivalent cells from opposite netlists. Some cells can have feed ports. The feed port is a port unconnected to devices of the cell. Guardian HLVS is ignored feed ports during LVS verification. But the equivalent cells from opposite netlists should have the same number of “real” ports (ports connecting to at least one device in cell by a net)
• Guardian HVLS can merge and reduce the devices connected in parallel or in series inside each cell, if corresponding options are selected. If the cells from compared netlists are recognized as hierarchically equivalent, the content of these cells is ignored and the reduction operations for their elements are inadmissible
• HLVS can handle the primitive port swappability. The logical equivalence of gates of complex logical elements obtained in reduction stage can be carried up from transistor level to respective ports of cell. Also special cases of port swappability can be recognized (for details, see section 5)

3. Hcells

Abbreviation Hcell is used for hierarchically compared cells. You can specify the pairs of hierarchically compared cells in initial correspondence file by statement

.HCELL =< LaySubckt >,

where SchSubckt is the name of subcircuit in schematic netlist, and LaySubckt is name of subcircuit in layout netlist. It’s expected that the Hcells exist in both netlists and the cells of each pair are equivalent. A pair is ignored if a subcircuit of this pair does not exist in a netlist. HLVS verification is performed for each pair, and the hierarchically equivalent cells can be used later in verification as whole blocks without considering their contents. Also you can specify the top cells in initial correspondence file by the statement