HiSIM (Hiroshima university STARC IGFET Model) is one of the surface potential based Spice models [1], [2] and pioneered the iterative approach to obtain the surface potential applicable in compact models. The model aims for MOSFET technology of 100 nm or below. The parameter extraction procedure was introduced first by the model developers: Semiconductor Technology Academic Research Center (STARC) [3], [4]. Silvaco UTMOST-III introduced the first version of the local optimization strategies for HiSIM-1.1 in 2002 [5]. Since then, the parameter extraction methodology has been reviewed thoroughly. This article is meant to provide significant aspects on the HiSIM version 1.2 parameter extraction for UTMOST-III users.

In this article, we describe practical behavioral modeling for highly non-linear circuits using Verilog-A, which is analog extension of Verilog-AMS. At first, we describe behavioral modeling techniques for phase/frequency detectors (PFD) and voltage-controlled oscillators (VCO) those are essential part of phase-locked loop systems shown in Figure.1. Model parameter extraction techniques are described and demonstrated later. Finally, these models are simulated with SmartSpice and verified against the results of transistor circuit simulations.

HIPEX-Net is a hierarchical layout extractor. It can create both hierarchical and flat SPICE formatted netlists of the extracted layout. HIPEX-Net also performs ERC (Electric Rule Checking) on the extracted netlist. This checks for connectivity errors in a chip design such as opens, shorts, and dangling nodes.

This article presents an overview of new features added to Silvaco’s Expert layout editor. Silvaco has taken a careful look at the real-world obstacles faced daily by semiconductor layout designers and design engineers. Silvaco has augmented Expert with features that dramatically increase flexibility and also help to reduce constraint violations and other roadblocks inherent to complex layout design.