Entries by Graham Bell
Victory TCAD Suite: How to use it for fast, efficient, and accurate simulation of power semiconductor devices
Silvaco TCAD has been used by Tier 1 power device manufactures and designers for decades. The introduction of Victory Process, Victory Mesh, and Victory Device significantly increases the functionality and flexibility of the tool set available to designers. In this article we look at how some of the features of this suite of tools improve the efficiency of the design flow.
TCAD Simulations of RF-SOI Switches with Trap-Rich Substrate
The market for cellular components has been shifting rapidly from GaAs pHEMT or silicon-on-sapphire (SOS) to silicon-based technology. CMOS (silicon-on-insulator) SOI antenna switches which are compatible with multimode GSM/EDGE, TD/WCDMA, and LTE systems exhibit higher integration levels and have become the fastest growing mobile phone submarket. CMOS-SOI processes, especially with thin silicon, have the potential to rival the FoM that was traditionally feasible only with GaAs technologies.
Hints and Tips: Specify Units in the Victory Process Material Statement
It is crucial for any kind of calculations that units are consistent between equations and modeling modules. Often different units are used in various experimental and theoretical fields. Therefore, we have introduced standardized unit conversions, making it possible to specify any desired units when changing parameters within the MATERIAL statement.
Hints and Tips: How do I Load, Remesh, and Refine an Existing Device Structure in Victory Mesh?
Victory Mesh initially supported loading and remeshing of the saved status from Victory Process. Victory Mesh 1.5.0 onwards is now able to load and remesh individual structure files (.str files), including associated scalar fields. These include the result of a device simulation from software such as Victory Device and Atlas.
Two-dimensional oscillatory neural networks for energy efficient neuromorphic computing
Feb. 5, 2020
On the 4 th and 5th of February 2020, in Montpellier (France), at the premises of LIRMM, CNRS the Kick-off meeting of NeurONN took place. All the Partners of the NeurONN Consortium met and set the ground for the activities along the three-year duration of the EU Project
IBIS Models in SmartSpice
The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which is affiliated with the Electronics Industry Alliance (EIA). These models are suitable for high-speed designs of digital systems to evaluate Signal Integrity issues (deformation of electronic signals, cross-talk, power/ground bounce, transmission lines…) on printed circuit boards (PCBs).