Speaker:

Dr. Babak Taheri, Chief Executive Officer and Board Member
Silvaco, Inc.

Babak Taheri is the CEO and Member of the Board of Directors at Silvaco Group, a leading provider of TCAD, EDA, and design IP software. He began his career at Silvaco as chief technical officer and executive vice-president of products. He also has been the CEO / president of IBT working with investors, private equity firms, and startups on M&A, technology, and business diligence.

While at IBT, he served on advisory boards of MEMS World Summit, Novasentis, AGCM, ALEA labs, Lion Point Capital, and Silver Lake. Prior to IBT, he was the VP & GM of the sensor solutions division at Freescale semiconductor (now NXP).

Babak was the recipient of “The Perfect Project Award” in 2003 while at Cypress; Twice recipient of the “Diamond Chip Award” in 2013 /14 while at Freescale; recipient of the MEMS & Sensors executive of the year award in 2014, and in 2015 was the recipient of the Distinguished Engineering Alumni Medal from UC. Davis College of Engineering, where he is on the advisory board to the college. Dr. Taheri served as a member of the governing council on ESDA Alliance from 2019 to 2021 and served on the board of Parisi House on The Hill from June 2021 to May 2022.

He has held VP/GM roles at Cypress Semiconductors, Invensense (now TDK) and key roles at SRI International and Apple. Babak received his Ph.D. in biomedical engineering from UC Davis with majors in EECS and Neurosciences. He has over 20 published articles and holds over 30 issued patents. His most recent published book in 2021 is titled “Artificial Sensors Shape the Six Pillars of Our Lives”.

Design and Optimization of Superconducting Circuits

Abstract:

Superconducting electronics (SCE) provides us with a variety of methods for speeding-up computation, and it suits well the implementation of data flows and machine learning algorithms. SCE is implemented in various forms and styles, and these imply new and different constraints for logic design. This talk will show the relations between circuit styles, design constraints and synthesis, in the search for laying a framework for designing SCE tool flows in diverse ways. Recent results and achievements will also be presented.

Speaker:

Prof. Giovanni De Micheli
École Polytechnique Fédérale de Lausanne (EPFL), Switzerland

Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at École Polytechnique Fédérale de Lausanne (EPFL), Switzerland.

Designing Extreme Scale Machine Learning Hardware

Abstract:

Custom ASICs are key for accelerating machine learning. These dedicated IP consumes a few milliwatts in smart phones, a dozen watts in automotive applications, and many kilowatts when training large ML models. Cerebras has developed a unique wafer-scale ASIC that is the heart of an ML supercomputer. This Wafer Scale Engine contains a whopping 2.4 trillion (with a T) transistors. We’ll cover the software flow that maps PyTorch models onto this massive chip. Just like a conventional ASIC design flow, this includes synthesis, placement and routing, but with a twist.

Speaker:

Patrick Groeneveld
Ph.D, Cerebras Systems

Patrick Groeneveld works at Cerebras Systems, a machine learning hardware startup that makes the world’s first monolithic supercomputer. Before that he worked for many years in the EDA industry. He was Chief Technologist at Magma Design Automation where he was part of the team that developed a groundbreaking RTL-to-GDS2 synthesis product. Patrick was as also a Full Professor of Electrical Engineering at Eindhoven University. He is a lecturer in the EE department at Stanford University and serves as finance chair in the Executive Committee of the Design Automation Conference. Patrick received his MSc and PhD degrees from Delft University of Technology in the Netherlands.

TCAD Simulation Update

Abstract:

Dr. Guichard will provide an update on Silvaco TCAD Victory simulation products, the importance of TCAD in the development of next-generation devices, and the future of TCAD development.

Speaker:

Dr Eric Guichard, Senior VP and GM of TCAD Division
Silvaco, Inc.

Dr. Eric Guichard is Vice President of Silvaco’s TCAD Division. He is responsible for managing all aspects of the TCAD division from R&D to field operations. Since joining Silvaco in 1995, he has held numerous positions including director of Silvaco France and most recently Director of Worldwide TCAD Field Operations. Prior to joining Silvaco, Guichard was a senior SOI engineer specializing in transistor and circuit aging at LETI and Thomson Military and Space.

Dr. Guichard holds an MS in material science and a Ph.D in semiconductor physics from Ecole Nationale Polytechnique de Grenoble, France.

Revised Mobility Model for Predictive TCAD Simulations of 4H-SiC

Abstract:

Development of energy efficient next generations of Silicon Carbide (SiC) power MOSFETs is necessary to meet a growing demand for SiC technology from a wide range of applications that includes electric vehicles, solar inverters, power supplies, industrial motor drives and energy storage etc. Success of R&D efforts critically depends on ability to perform predictive TCAD simulations of SiC power MOSFETs. Although significant progress has been made in TCAD modelling of 4H-SiC, we observe that the existing set of models needs further improvements and calibration.

In this presentation, we focus on the bulk mobility model for 4H-SiC. We observe that the temperature dependence of bulk resistivity cannot be predicted accurately using the popular mobility models. A careful investigation reveals that these mobility models need to be revised and replaced by a comprehensive model that can describe the impurity scattering effects dominant at low temperatures. We present a well calibrated bulk mobility model for 4H-SiC exhibiting excellent agreement with measured data, making it suitable for device simulation purposes using TCAD tools.

Speaker:

Hemant Dixit, Ph.D.
Research Scientist, Wolfspeed, Inc.​​

Hemant holds PhD in Physics from University of Antwerp, Belgium and has been working in the Semiconductor industry for 10+ years. Prior to joining Wolfspeed, he worked at MOTOROLA, IBM and GLOBALFOUNDRIES. His expertise includes multiscale (both atomistic and continuum) modelling of semiconductor devices using TCAD tools. Hemant has published over 35 research articles with 1700+ citations and filed 15 patent applications (6 approved) with USPTO. At Wolfspeed, his focus is on improving the fundamental understanding of power MOSFETs, to accelerate the design and development efforts for next generation of devices.

TCAD as a Key Enabler for Photodiode Design

Abstract:

Photodiodes are a key technology to many growing application areas. Automotive vision systems, Advanced industrial machinery, and high-speed communications systems all rely on photodiodes to link optical inputs into usable electrical signal.

In this talk Silvaco will discuss these technologies, and how TCAD can be broadly applied to multiple detector topologies/material sets and thus multiple end-user markets. Additionally, we’ll detail simulation and analysis of an InGaAs Avalanche Photodiode. Through this demonstration, it will be shown how TCAD can be used to explore and characterize diode performance and extracting key Figures of Merit. Through TCAD, photodiode designers and technologists can increase their device performance, while decreasing engineering manufacturing and test cycles.

Speaker:

Sungwon Kong, Sr. Staff Field Applications Engineer
Silvaco, Inc

Sungwon Kong  has been supporting TCAD applications for digital displays beginning at Silvaco Korea in 1996. He graduated from Inha University in electrical materials and device engineering and worked at Samsung Electronics at Gi-heung, Kung-gi-do before joining Silvaco.

Advanced Modeling Solutions for Accelerated Technology Development and Manufacturing

Abstract:

Speaker:

Sumeet Pandey, Senior Member of Technical Staff
Micron​

Behavior of FinFET at Very Low Temperatures and Creation of Qubits

Abstract:

Quantum effects are dominant on the nanoscale which classical simulation tools cannot even observe. In Ciena, our Analog design process is heavily dependent on provided models but as we scale, these models get less accurate. As a result, we have started analysis and verification to create our own models to account for quantum effects. Another requirement for Ciena is to analyze the behavior of devices in cryogenic temperatures to conduct research on Qubit technology.

For quantum device modeling, specialized tools capable of solving Poison-Schrodinger equations self-consistently are required. Silvaco’s Victory Atomistic (ViA) tool met the basic requirements. However, we soon realized many details needed to be worked out, leading to close collaboration of Silvaco and Ciena teams.

As a result of Silvaco-Ciena’s teamwork, we now have an engine that simulates Ciena’s in-house devices precisely, i.e., we match the ViA results with already obtained lab results of the 5nm devices at room temperature.
On the Qubit technology front, we were already able to measure and observe device behavior in extreme low temperatures, but the process was costly and complex. We needed to replace the measurement process with device simulation where Silvaco’s ViA seems to be a good candidate. Future work involves improving ViA in several directions. Convergence in lower cryogenic temperatures is one such direction where ViA holds a huge promise.

Speaker:

Sanam Moslemi-Tabrizi, Hardware Engineer
Ciena​

Sanam Moslemi-Tabrizi received her B.Eng. degree in Electrical Engineering with a focus on Analog Circuits from Tabriz University in 1996. She earned her M.Sc. degree in Electrical Engineering with a focus on Solid State Devices from Concordia University in 2007. Her master’s thesis was on Computational Quantum Mechanics where she computed Eigenstates for Multi-Dimensional Nanostructures. As a Research Associate with the department of Electronics at Carleton University she has conducted research on Electromagnetic and worked on the development of an OPA based 2D beam scanning for LiDAR applications. To aid her research on EM, she developed a Full Vectorial Mode Solver and Waveguide Simulator based on Yee cell FDFD. Currently she is an Analog Engineer at Ciena working on verification and optimization of analog circuits, as well as developing Quantum Device Models for Ciena’s next generation products.

Performance Improvement for Cu Interconnects by SAM and ELD Technologies

Abstract:

An effort to improve the properties of semiconductor BEOL interconnects is introduced.

The combination of SAM, which is selectively deposited on materials, and ELD technology, which allows selective metal growth, can improve the properties of semiconductor devices.

Experimental results and Silvaco simulation results show a trend in agreement, indicating the usefulness of this process.

Speaker:

Yuki Kikuchi
Tokyo Electron Limited​

Yuki Kikuchi joined Tokyo Electron Limited in 2011 after graduating from the University of Tsukuba and has been with the company for 12 years. He belongs to Corporate R&D and is engaged in fundamental technology, BEOL process, 3DI, and process integration development.

Victory Atomistic – Updates on 2D Materials, CNTs, and How We Bridge Atomistic Simulations and TCAD

Abstract:

Performance predictions of nanodevices ideally include 1) atomistic resolution, 2) a consistent description of all quantum phenomena, and 3) a realistic treatment of incoherent scattering on phonons and impurities. It is common believe that atomistic quantum transport either entails unfeasible numerical load or neglects scattering effects altogether. Victory Atomistics indeed covers all 3 aspects, and this presentation showcases new modeling features in the realm of 2D materials and carbon nanotubes.

While Victory Atomistic covers all those points for only a small fraction of the typical numerical costs, some of the atomistic simulations might still take a few CPU hours to finish. Therefore, Silvaco’s and Purdue’s teams are bridging the gap between atomistic simulations and TCAD to enable reliable simulation results in TCAD typical simulation times.

Speaker:

Tillmann Kubis
Katherine Ngai Pesic and Silvaco Research Associate Professor of Electrical and Computer Engineering
Purdue University

Prof. Dr. Tillmann Kubis is leader of Purdue’s NEMO5 development team. His research interest includes all topics of equilibrium and non-equilibrium phenomena in nanodevices and molecules. This covers electronic and phonon bandstructures as well as heat, charge, and spin transport in nanodevices. Dr. Kubis holds a Dr. rer. nat. in theoretical semiconductor physics from the Technische Universität München, Garching, Germany.

Achieving Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory TCAD Solution

Abstract:

When employing process simulation to generate a complex device structure, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco Victory Process offers several geometric models to efficiently achieve etch geometries that accurately match microscopy images (e.g., transmission electron microscopy).

In this webinar, we present these geometric etch models in the context of FinFET and memory applications. We demonstrate techniques to realize fin shaping, non-ideal etch profiles (bowing, twisting), and self-aligned processes (multi-patterning).

Speaker:

Alexander Toifl, Development Engineer
Silvaco, Inc.​

Since joining Silvaco in 2021, he has worked on etch and deposition models in Victory Process. Alexander Toifl received a doctoral degree in electrical engineering from the University of Technology Vienna (TU Wien), Austria, and a M.S. degree in microelectronics and photonics from the same institution.

Advanced Flux Models in Victory Process: Low-Bias SF₆ Etching and Thermal Atomic Layer Processing

Abstract:

The accurate simulation of topographies resulting from semiconductor processing techniques requires comprehensive physical modeling. The reactive transport models, that is, the interactions of the particle fluxes and the surface kinetics, must be carefully considered. This is the case even for the seemingly simple processing techniques which are described by a single, uncharged particle, such as low-bias SF₆ etching and thermal atomic layer deposition and etching.

In this talk, we present an overview of phenomenological single-particle models for process TCAD with a focus on the impact of the chosen flux model on the simulated topography. The existing flux models in Victory Process are introduced, as well the advanced models developed by the Christian Doppler Laboratory for High Performance TCAD. For low-bias SF₆ etching, we propose a Monte Carlo method, currently prototyped within Victory Process. For the more complex chemical reactions in thermal atomic layer processing, we implement a one-dimensional Knudsen-Langmuir model completely within the Open Model Library, highlighting the powerful user-extensibility of Silvaco TCAD.

Speaker:

Luiz Felipe Aguinsky, Researcher
Christian Doppler Laboratory for High Performance TCAD, Institute for Microelectronics, TU Wien

Luiz Felipe Aguinsky was born in 1990 in Porto Alegre, Brazil. He received his Bachelor’s degree in Physics from the Federal University of Rio Grande do Sul (BSc, 2013). Subsequently, he studied Simulation Sciences at RWTH Aachen University (MSc, 2018), having written the Master’s thesis at the German Aerospace Center. After finishing his studies he joined the Institute for Microelectronics in March 2018, where he is currently finishing his doctoral degree. Afterward, he will join ETH Zurich on a Schrödinger Fellowship. His research interests are phenomenological models for Process Technology CAD, atomic layer processing, and related devices such as valence-change memories.

Analog Custom Design Update

Abstract:

Thomas Blasei will provide an update on Silvaco’s Analog Custom Design product portfolio, new features and functionality, and the future of Silvaco’s EDA solutions.

Speaker:

Thomas Blaesi, VP and GM of EDA Division
Silvaco, Inc​​​

Thomas F. Blaesi is Vice President and General Manager of the EDA Business Unit. He is responsible for managing the development of all EDA tools including analog customer design, circuit simulation and SPICE modeling. Thomas joined Silvaco in October 2017 and held the position of Vice President of Global Marketing until December 2019. He has more than 25 years of experience in corporate strategy, business development, and marketing in semiconductor, and electronic design automation industries. He has led major projects in SoC platform-based design, system-level design, and design for manufacturing in addition to hands-on experience in custom and semi-custom chip design and development.

Most recently, Thomas was the managing partner at Zeema Technologies. Before that, he served as CEO of Chipvision, and held various senior business and technical positions at Cadence, Synopsys, and LSI Logic.

Thomas holds a BS in electrical engineering and computer science from Hochschule Furtwangen University, Germany.

Advances in Device Modeling Using Utmost IV

Abstract:

In this session Silvaco will present some of the 2022 Baseline enhancements to our Utmost IV Device Modeling tool. We will introduce the Corner and Retargeting Module, the most recent addition to our modeling software platform, and review some of the newest models and technologies where Silvaco’s Utmost IV is a key contributor. The presentation will conclude with a review of Silvaco’s modeling services through which our customers can benefit from our extensive SPICE modeling expertise.

Speaker:

Bogdan Tudor, Senior Manager, Device Characterization
Silvaco, Inc.​

Bogdan Tudor is Head of Device Characterization for Silvaco, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software.

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A Robust 3nm to 350nm Design Flow Utilizing Silvaco Tools

Abstract:

Chung-Chun Chen will go through an overview of Silicon Creations and our role as an IP vendor, which may include our achievements and products. The front-end challenges and solutions will be discussed, including our use of Gateway in addressing porting challenges between 12 different foundries in 180nm down to 3nm nodes. Then the back-end challenges and solutions will be also addressed, including our use of Expert. The final simulation challenges and solutions include our use of SmartSpice, Silos, and Variation Manager. This talk shows using Silvaco tools helps Silicon Creations’ IP development be efficient and robust from 3nm to 350nm.

Speaker:

​​​Chung-Chun Chen, Director of Analog Design
Silicon Creations 

Chung-Chun (CC) Chen has been with Silicon Creations since 2011 and is a principal circuit architect for SerDes IO interface. Currently, CC leads SerDes team as a Director of Analog/Mixed-Signal Design at Silicon Creations in Atlanta, Georgia since being back in 2019. During 2018 – 2019, CC joined Ubilinx Technology (Realtek Semiconductor Group) in San Jose, CA, and he was the driver/architect of Realtek’s high-speed Serdes technologies. During 2011 – 2018, CC was a senior analog designer/manager at Silicon Creations in Atlanta, Georgia while he designed analog IP products including Ring-based & LC tank PLLs, Serializer, De-serializer with all clocking building blocks (PLL/CDR, phase interpolator) and equalization (FFE, CTLE, DFE) circuitry. Before joining Silicon Creations, he was a research staff member at Samsung Electro-Mechanics design center in Atlanta, Georgia. Prior to this, he was a principal engineer at TSMC in Hsinchu, Taiwan, where he worked on clocking architecture design and related customer support.

Chung-Chun (CC) Chen (S’02–M’09–SM’17) was born in Taipei, Taiwan, in 1979. He received the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2004 and 2009, respectively. His current research interests focus on circuit designs in clocking and other SerDes building blocks for high-speed communication systems. He has published over 15 papers in peer-reviewed conferences and journals. He is a Senior Member of the IEEE and served as a reviewer of JSSC and T-MTT.

Advanced TFT-Based Flat Panel Design with SmartSpice

Abstract:

This talk covers two extremely important aspects related to the design and simulation of Flat Panel Displays: 4-terminal TFT devices, and image retention.

Many TFT technologies in the market today are based on 4-terminal devices. In contrast, the SPICE simulators from other vendors can only support 3-terminal TFT compact models. Silvaco’s 4-terminal TFT model is unique in the market, and we will present some of the characteristics of this compact model, and some of the degrees of freedom that it brings to both modeling and the design teams.

Additionally, image retention is a long-standing issue in the display community. To effectively solve this issue, or even to minimize its impact on their products, display manufacturers and consumer electronics vendors need to simulate this effect at the SPICE level. We describe how SmartSpice Flex Modeling technology can be used to simulate image retention issues. This solution, which is unique to Silvaco, can model any dynamic device effects in SPICE simulation.

Speaker:

Jody Matos, Director of Circuit Simulation
Silvaco, Inc.

Dr. Jody Matos is a Ph.D. Computer Scientist who is passionate about research and development of software and hardware designs. Currently, he is the Director of Circuit Simulation at Silvaco, where he has been managing leading-edge R&D and business-related projects for EDA tools. His current tasks are mainly related to circuit simulation and analyses on analog, digital, and mixed-signal IC designs.

Dr. Matos received a Ph.D. degree in computer science from the Federal University of Rio Grande do Sul (UFRGS), Brazil, and a M.S. degree in microelectronics from the same institution. He has co-authored 30+ research papers and patent applications that mix knowledge of both computer science and microelectronics. Dr. Matos has also served as an expert reviewer and on technical committees of several renowned journals and international conferences in the fields of design automation.

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Silvaco SmartDRC/LVS: A Powerful, User Friendly and Flexible Layout Verification Solution

Speaker:

​​​Richard Lum, CEO
MPics Innovations Pte. Ltd.

Richard Lum, (M’88-SM’10) received his B.ENG in EE (88) from the National University of Singapore and his MBA (98) from the UK Open University.

Richard Lum is the CEO, Co-founder and Microchip Architect of MPics Innovations Pte Ltd which specialises in custom analog circuit design and manufacturing. He has more than 20 patents in the field of analog circuits and isolation technology. His current interests involve the design and development of new and novel methods of signal communications across galvanically isolated barriers in multi-chip modules and has filed a patent for a new isolation method suitable for broadband power devices such as GaN and SiC. Richard is also an industrial entrepreneur and has successfully started-up integrated design companies in Singapore for Aztech Systems and for BlueChips Technology which subsequently IPO in Malaysia’s MESDAQ Board. Prior to MPics, he was the Senior Director of R&D for Broadcom’s Isolation Products Division responsible for product definition, technology development, product design and development of advanced optical and non-optical isolation devices for Industrial and EV Markets. He is a Senior Member of IEEE.

VarMan Delivers Unprecedented High-Sigma Performance within a User-Friendly GUI Environment

Abstract:

Accuracy and flexibility have always been the core of VarMan technology. Today with the latest GUI redesign and algorithm enhancements, VarMan is entering a new era providing major improvements to the user experience that benefits from a wide customers’ feedback gathered along  years of worldwide deployment.

This new baseline version will be able to keep addressing new challenges and make variation analysis accessible to a larger audience.

Speaker:

Vincent Annezo, VarMan Corporate Application Engineer
Silvaco, Inc​​​.

Vincent is a Corporate Application Engineer dedicated to VarMan improvement and support. Prior to Silvaco, he worked as a Software Validation and Application Engineer at Aselta (French EDA start up) for 9 years. He earned a Master of Engineering degree in physics in 2003 from the engineering school INSA in Rennes, France.

Latest Update on Interconnect Parasitic Reduction and Analysis with Jivaro and Viso

Abstract:

In this presentation we will present the new features developed in Jivaro (parasitic reduction) and Viso (parasitic analysis and exploration) to tackle various challenges related to post layout interconnect parasitics. Latest Jivaro with its new “Pro” module is taking the parasitic reduction to a new era and enables unprecedented speed of SPICE simulations, especially for advanced process nodes. Viso has been enriched with new features to enable fast understanding and debug of parasitic structures without the need for long simulations.

Speaker:

Simon-Alexis Abric, Corporate Application Engineer
Silvaco, Inc.

Mr. Simon-Alexis Abric is a Corporate Application Engineer for Silvaco France. He is responsible for customer technical support for reduction (Jivaro) and parasitic analysis (Alps) products. Prior to Silvaco, he was an Application Engineer at Edxact SA for four years.

Mr. Abric earned a Master of Engineering degree in integrated circuits and systems in 2013 from the engineering school ENSEIRB in Bordeaux, France.

Design IP Solutions Update

Abstract:

Ben Louie will provide an update on Silvaco’s portfolio of Design IP, and its direction for the future.

Speaker:

Ben Louie, Associate Vice President of Foundation IP​
Silvaco, Inc​​​.

Ben Louie has over 22 years of experience in Memory Design including NOR Flash, NAND Flash, and MRAM. Most recently he was Director of Memory Design and Fellow at Spin Memory where he led their MRAM memory design efforts and was one of the primary inventors for their MRAM Engine IP. Prior to Spin Memory, Ben was Director of Design and Chief Design Engineer at Zeno Semiconductor where he worked on the development of a novel 1T SRAM memory. Additional startup experience also includes Magsil, a Field MRAM IP company. Before working startups, Ben worked at a few large semiconductor companies including Micron Technology and Xilinx. At Micron Technology, Ben led the Design team in the transition from NOR flash to NAND flash and was the design lead/manager for their first NAND products. Ben holds a Bachelor of Science Degree in Electrical Engineering and a Master of Science Degree in Electrical Engineering from Santa Clara University. He has been issued over 116 US Patents.

Implementing Debug for I3C

Abstract:

The Debug for I3C interface – Simplified Address-Mapped (SAM) debug add-on, is designed to allow for debug, trace, and perform test/failure analysis using an I3C peripheral. Using existing SCL and SDA pins of the I3C bus, it facilitates data transfer between the application and the peripheral that is being debugged. In this presentation, we discuss the details SAM debug add-on IP and connection to popular debug trace adapters such as ARM DAP, ARM-ETM/SWO, JTAG-TAP, RISC-V DMI/DM.

Speaker:

Ashish Senapati, Platform Debug Architect
Intel

Ashish Senapati is a Platform Debug Architect working in Client Computing Group at Intel Corporation. He has 10 years of experience as an SOC Architect for low power 8-bit microcontrollers and high performance wireless microcontrollers at Microchip Technology Inc. Prior to that he worked for 3+ years in application development using microcontrollers and FPGAs for CES demos and proof of concept designs for Altera (Intel), Microchip and Freescale (NXP).

Replacing an End-of-Life MCUP

Abstract:

Like any product, a microcontroller unit (MCU) has a life cycle – it has a beginning, it is sold on the market for a period of time, and it has an end. Some companies that rely on a specific MCU for their products have a significant investment in software that is not easily ported to another MCU. When a microcontroller approaches its end-of-life, these companies must decide how to replace the end-of-life microcontroller in their products.

This presentation will explore an option in which the purchasing company has decided to create a replacement for the end-of-life microcontroller. Design considerations and implementation choices will be discussed. Each chip replacement project is custom and requires a range of IP products to complete the functional replacement. Silvaco offers a range of IP products and design services to help with this effort.

Speaker:

Errett Hogrefe, Senior Digital Design Engineer 
Silvaco, Inc​​​.

Errett Hogrefe is a Senior Digital Design Engineer in Silvaco’s IP Division. Errett is the architect, developer, and supporter of many digital cores in Silvaco’s IP portfolio, including SPI, Quad-SPI and Octal-SPI Controllers. Errett joined Silvaco in 2017 and prior to joining Silvaco Errett was an engineer of various descriptions for 16 years at SoC Solutions.

Standard Cells and I/O Library Optimization and Validation

Abstract:

As an active semiconductor foundry, process or technology development and enhancement is frequent. To meet and verify the enhancement on library, library optimization and validation is needed.

In this presentation, we will share the challenges of optimizing and validating different libraries, and demonstrate how Cello, Viola and SmartSpice contribute in a unique, dynamic way to realize the optmization and validation, which ultimately results in reducing library development and validation time even though we have limited man power/resources.

Speaker:

Mr. Faris Amsyar Bin Ahmad Zhaki, IP Staff Engineer
SilTerra Malaysia Sdn. Bhd

Mr. Faris Amsyar Bin Ahmad Zhaki is an IP Staff Engineer with SilTerra focusing on Standard Cell and I/O library development and silicon validation for over 5 years. Mr. Faris Amsyar Bin Ahmad Zhaki holds a Bachelor of Electronics Engineering from University of Science, Malaysia.

Standard Cells and I/O Library Optimization and Validation

Abstract:

As an active semiconductor foundry, process or technology development and enhancement is frequent. To meet and verify the enhancement on library, library optimization and validation is needed.

In this presentation, we will share the challenges of optimizing and validating different libraries, and demonstrate how Cello, Viola and SmartSpice contribute in a unique, dynamic way to realize the optmization and validation, which ultimately results in reducing library development and validation time even though we have limited man power/resources.

Speaker:

Nur Liyana Binti Jasn, IP Staff Engineer
SilTerra Malaysia Sdn. Bhd

Ms. Nur Liyana Binti Jasni is an IP Staff Engineer with SilTerra focusing on Standard Cell and I/O library development and silicon validation for over 11 years. Ms. Nur Liyana Binti Jasni holds a Bachelor of Science in Electronics & Computer Engineering from Hanyang University, South Korea.