A Robust 3nm to 350nm Design Flow Utilizing Silvaco Tools
Chung-Chun Chen will go through an overview of Silicon Creations and our role as an IP vendor, which may include our achievements and products. The front-end challenges and solutions will be discussed, including our use of Gateway in addressing porting challenges between 12 different foundries in 180nm down to 3nm nodes. Then the back-end challenges and solutions will be also addressed, including our use of Expert. The final simulation challenges and solutions include our use of SmartSpice, Silos, and Variation Manager. This talk shows using Silvaco tools helps Silicon Creations’ IP development be efficient and robust from 3nm to 350nm.
Chung-Chun Chen, Director of Analog Design
Chung-Chun (CC) Chen has been with Silicon Creations since 2011 and is a principal circuit architect for SerDes IO interface. Currently, CC leads SerDes team as a Director of Analog/Mixed-Signal Design at Silicon Creations in Atlanta, Georgia since being back in 2019. During 2018 – 2019, CC joined Ubilinx Technology (Realtek Semiconductor Group) in San Jose, CA, and he was the driver/architect of Realtek’s high-speed Serdes technologies. During 2011 – 2018, CC was a senior analog designer/manager at Silicon Creations in Atlanta, Georgia while he designed analog IP products including Ring-based & LC tank PLLs, Serializer, De-serializer with all clocking building blocks (PLL/CDR, phase interpolator) and equalization (FFE, CTLE, DFE) circuitry. Before joining Silicon Creations, he was a research staff member at Samsung Electro-Mechanics design center in Atlanta, Georgia. Prior to this, he was a principal engineer at TSMC in Hsinchu, Taiwan, where he worked on clocking architecture design and related customer support.
Chung-Chun (CC) Chen (S’02–M’09–SM’17) was born in Taipei, Taiwan, in 1979. He received the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2004 and 2009, respectively. His current research interests focus on circuit designs in clocking and other SerDes building blocks for high-speed communication systems. He has published over 15 papers in peer-reviewed conferences and journals. He is a Senior Member of the IEEE and served as a reviewer of JSSC and T-MTT.