Colin Shaw of Silvaco Named Si2 Pinnacle Award Winner
December 12, 2021
这位作者还没有写个人简历。
我们为 Gigi Boss 对 401 篇日志做的贡献感到骄傲。
December 12, 2021
Abstract— Silvaco TCAD simulations are employed to identify relevant current carrying mechanisms in amorphous selenium (a-Se) based detectors, using parameters obtained from experimental data, density functional theory calculations, and in-house bulk Monte Carlo simulations. The steady-state dark current behaviors in various a-Se detectors are analyzed by identifying all relevant current conduction mechanisms (e.g., space-charge limited current, bulk thermal generation, Schottky emission, Poole-Frenkel activated mobility and hopping conduction), as well as “acceptor” and “donor” defect density of states located in the forbidden band gap of a-Se. The theoretical models are validated by comparing them with experimental steady-state dark current densities in avalanche and non-avalanche a-Se detectors.
Location: Seattle/Bellevue, WA – Boston, MA – Phoenix/San Diego, CA
As a Strategic Account Manager at Silvaco, you will be responsible for generating new business for our full line of EDA, TCAD, and IP products.
Location: Seattle/Bellevue, WA – Boston, MA – Phoenix/San Diego, CA
As a Strategic Account Manager at Silvaco, you will be responsible for generating new business for our full line of EDA, TCAD, and IP products.
Abstract— A Singular Point Source MOS (S-MOS) cell concept suitable for power MOS based devices is presented. The S-MOS differs from a standard Planar or Trench MOS cell in the manner by which the total channel width per device area is devised. The S-MOS single cell channel width is defined as the peripheral length of a line running approximately along the N++ source and P channel junction which is positioned on a gated trench side-wall. The length of the line is established from a singular point implant source for forming the N++ source region which geometrically corresponds to the shape of the N++/P junction. The N++ and PChannel profiles achieved are similar to those for a planar cell, but for the S-MOS, they are situated on a trench side-wall. The total device channel width will therefore depend on the total number of gated trench side-walls per chip. The S-MOS provides a unique approach for MOS cell layout designs and is applicable to different MOS based power devices. In this paper, the S-MOS is implemented on a 1200V IGBT by means of 3D-TCAD simulations while providing results highlighting the potential advantages with respect to the device static and dynamic performance.
Keywords – MOS cell, Insulated gate bipolar transistors.
Abstract— A Singular Point Source MOS (S-MOS) cell concept suitable for power MOS based devices is presented. The S-MOS differs from a standard Planar or Trench MOS cell in the manner by which the total channel width per device area is devised. The S-MOS single cell channel width is defined as the peripheral length of a line running approximately along the N++ source and P channel junction which is positioned on a gated trench side-wall. The length of the line is established from a singular point implant source for forming the N++ source region which geometrically corresponds to the shape of the N++/P junction. The N++ and PChannel profiles achieved are similar to those for a planar cell, but for the S-MOS, they are situated on a trench side-wall. The total device channel width will therefore depend on the total number of gated trench side-walls per chip. The S-MOS provides a unique approach for MOS cell layout designs and is applicable to different MOS based power devices. In this paper, the S-MOS is implemented on a 1200V IGBT by means of 3D-TCAD simulations while providing results highlighting the potential advantages with respect to the device static and dynamic performance.
Abstract—During the last few years, oxide-based ReRAM technology has attracted intense industrial and scientific research interest. Therefore, we have performed an in-depth computational study with a focus on data retention besides the resistive switching and the current run-away. Our newly developed comprehensive TCAD (Technology Computer Aided Design) model provides deep insight into the underlying microscopic processes and is validated against experimental data as an accurate and predictive simulation tool.
Sept 2, 2021
September 9, 2021 | 10:00 am – 10:30 am (PDT)
This webinar will focus on a specific class of memory devices – targeted to mobile and IoT applications – that use “SPI” (Serial Peripheral Interface) signaling.
August 19, 2021 | 10:00 am – 10:30 am (PDT)
In this webinar, we present the top 10 new features and improvements enabled by the SmartSpice team during this past year.
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