One of the new features in Victory Device is the ability to add user managed parameters to a log file. This can be used when sweeping parameters (manually or in a Deckbuild loop), such as doping, stress, or layer thicknesses, to add the swept parameter to a log file. To do so, simply create a USER probe (with an optional name), and set the parameter USER on the MODELS statement to some value. This parameter (and value) will be added to the log file. The available user parameters are USER1, USER2, USER3, and USER4. The following shows a DeckBuild loop (go victoryd) to simulate the effect of varying STRESS_XX on the mobility.
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Entries by Gigi Boss
September 22, 2022
In this webinar we will introduce Victory Visual, a new graphical post-processing tool for use with all Silvaco TCAD simulators and an integral part of the TCAD Victory interactive tools suite.
The FET physical dimensions continue to shrink to five nm node and below, characterized by new types of architectures with nanosheet (NS) and nanowire (NW) shapes . The present choice of material is made of Si, Ge, or SiGe alloy thanks to their high carrier concentrations. In compliment to III-V technology envisaged for a while, new 2D materials are also investigated (for example, the TMDs monolayers1). Such nanomaterials and nano-architectures require atomistic simulations for at least two crucial reasons: 1) bulk parameters like the effective masses and forbidden bandgap are no longer pertinent quantities, and 2) the wave nature of charge carriers becomes predominant for predicting transport characteristics including scattering events.
September 8, 2022
In this webinar, we present how ultra-scaled Field-Effect Transistor (FET) technology requires simulations at the atomic scale for designing the most advanced technological architectures at 5 nm node and below. We present in detail the Victory Atomistic solution for atomistic simulations.
New Features in the 2022 Baseline Release:
- Section 1: Process Simulation – New Features in 2022 Baseline Release
- Section 2: Device Simulation – New Features in 2022 Baseline Release
- Section 3: Victory Mesh – New Features in 2022 Baseline Release
- Section 4: Silver – New Features in 2022 Baseline Release
August 11, 2022
In this webinar, we present these geometric etch models in the context of FinFET and memory applications. We demonstrate techniques to realize fin shaping, non-ideal etch profiles (bowing, twisting), and self-aligned processes (multi-patterning).
This work reports on the design of a high efficiency InGaN-based two junction (2J) tandem solar cell via numerical simulation, operating at high temperatures (450o C) and under 200 suns for application in a hybrid concentrating solar thermal (CST) system. To address the polarization and band-offset issues for GaN/InGaN heterojunction solar cells, band engineering techniques are employed. A simple interlayer is proposed at the hetero-interface rather than using an In composition grading layer, which is difficult to fabricate. The base absorber thickness and doping concentration have been optimized for 1J cell performance, and current matching was imposed on the series constrained 2J tandem cell design. The simulation results show that the crystalline quality (short recombination lifetime) of current nitride materials is a critical limiting factor the performance of the 2J cell design at high temperatures. The theoretical conversion efficiency of the best devices can be as high as ~21.8% at 450o C and 200X based on the assumed material parameters.
June 30, 2022
In this webinar, we highlight how leading display and detector companies exploit the capabilities of Silvaco tools for schematic and layout editing, very accurate field solver-based parasitic extraction required by modern TFT technology, back-annotation of parasitic RC elements into the netlist, and fast and accurate SPICE simulations of large arrays of pixels.
June 9, 2022
In this webinar, we will introduce a solution to the long-standing issue in the display community of Image Retention and how to simulate this effect at the SPICE level.
- Design IP
- Foundation IP
- Standard Cell Library IP
- IP Management