Using Viso to Investigate, Analyze, and Solve Complex Parasitic Issues
As process geometries shrink, the number of parasitic elements in a design and the complexity of their structures grow exponentially. Unfortunately, using simulations to investigate and correct parasitic issues is a long and labor-intensive task that can lead to tape-out delays.
Silvaco’s Viso was specifically designed to address these issues by reducing simulation iterations to speed up your design flow, providing a broad set of analyses to help you quickly identify, understand, and resolve parasitic problems.
What You Will Learn:
For Management:
- An overview of Viso’s benefits and features
- How Viso can streamline parasitic analysis and post-layout verification
For Verification and Layout Engineers:
- How to explore and identify the root causes of parasitic-induced design issues
- A detailed demonstration of Viso’s capabilities using a high-speed LVDS block as an example
Presenter
Carlos Augusto Berlitz, PhD
Corporate Application Engineer (CAE), Silvaco Inc.
Carlos Augusto Berlitz, PhD, is a Corporate Application Engineer for RC parasitics analysis and reduction EDA solutions at Silvaco. He contributes to the support, testing, and planning of Silvaco’s EDA tools for RC parasitics analysis and reduction. Previously, he worked in circuit design and support for a variety of companies. Dr. Berlitz joined Silvaco’s EDA team in 2023.
He holds a PhD in Electronics, Electrotechnics, Automation and Signal Processing from INSA Lyon, France, an MS in Electrical Engineering from Grenoble Alpes University (UGA), France, and a BS in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Brazil.
WHO SHOULD ATTEND:
IC designers, CAD engineers, and managers who are looking to improve the productivity of their design flow.
When: Thursday April 24, 2025
Where: Online
Time: 10:00am Santa Clara
Time: 10:00am Beijing
Time: 11:00am Paris