TCAD Simulation of Leakage Through Threading Dislocations in GaN-based pn-diodes
Stefano Dalcanale, Michael J. Uren and Martin Kuball
Center for Device Thermography and Reliability (CDTR), H. H. Wills Physics Laboratory, University of Bristol, Bristol BS8 1TL, U.K.
Gallium nitride (GaN)-based devices for power electronics show superior performance in comparison to silicon carbide and silicon-based devices [1]–[3]. The development of vertical devices, like pn-diodes and power HEMTs results in higher power density and voltage handling. One of the key parameters of this technology is the dislocation density. This is lower in free-standing GaN-on-GaN epitaxy than in heteroepitaxial GaN growth on different substrates like SiC or Si, but still has a density of 104-106 cm-2 [4]. The diode reverse leakage seems to be related to the dislocation density, and it can be modelled with a Poole-Frenkel or a hopping conduction mechanism [5]. The Poole-Frenkel model is already implemented in the trap-assisted tunnelling model in Silvaco Atlas [6]. For the leakage in threading dislocations a variable-range hopping (VRH) model has been implemented in the simulator, based on Ref. [7].
This Simulation Standard article discusses the simulation of the vertical leakage in a GaN pn-diode adopting the new VRH model.
We will first show the model details, especially how it is related to the dislocation density. Then, we will discuss how the model fits the experimental data of the leakage current in reverse bias at different temperatures.
