Chiping Tu, General Manager
Silvaco, Taiwan
Chiping Tu is the General Manager of Silvaco Taiwan office. Since joining Silvaco in 2008, he has been in charge of sales for all Silvaco products in Taiwan and responsible of Silvaco Taiwan team management.
Chiping Tu holds a M.S in Electrical & Computer Engineering from University of Texas at Austin and a B.S. in Electrical Engineering from National Taiwan University.
Zhao Qingda, Managing Director
Silvaco Singapore
Zhao Qingda is the Managing Director of Silvaco Singapore office. He joined Silvaco in May, 2005. Currently he is in charge of Silvaco Singapore management and sales of Silvaco products in Singapore, Australia, South East Asia.
Zhao Qingda holds a Bachelor’s and Master’s degree from School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore.
Dr. Babak Taheri, Chief Executive Officer and Board Member
Silvaco, Inc.
Babak A. Taheri, Ph.D., has served as Silvaco’s Chief Executive Officer and member of Silvaco’s board of directors from August 2019 to September 2021 and from November 2021 to present. From October 2018 to August 2019, Dr. Taheri served as Silvaco’s Chief Technology Officer and Executive Vice President of Products. Prior to joining Silvaco, Dr. Taheri served as Chief Executive Officer and President of Integrated Biosensing Technologies (IBT), an advisory and consulting firm, from May 2015 to October 2018. Dr. Taheri has also served on various advisory boards, including MEMS World Summit, a conference for MEMS manufacturers, equipment and material suppliers and research institutes, Novasentis, Inc., an electromechanical polymer technology development company, and as the advisory board chair of the electrical engineering department at the University of California, Davis. Dr. Taheri also served on the board of directors of Parisi House on The Hill, a residential alcohol and drug non-profit, from June 2021 to May 2022. Dr. Taheri received a B.S. in engineering from San Francisco State University, a M.S. in electrical engineering from San Jose State University and a Ph.D. in biomedical engineering from the University of California, Davis.
The EDA design flow uses a complex chain of algorithms to transform a functional description into a mask pattern. Some of the algorithms use numerical solvers, others are just clever heuristics that have proven to work. Each algorithm has a large variety of parameters that are hand-tuned tuned for best results. For instance, area and speed are traded off using relative cost parameters. Some recent tools apply Machine learning to automatically converge quickly on a design-specific set of parameters. This is done by brute force running the flow many times and using PPA data to discover the gradients.
Research work is done on making true ML-driven EDA tools. Some address placement, other routing strategies. In this presentation we will address the state of the art of ML in EDA flows and present an outlook of its impact in the coming decade.
Dr. Patrick Groeneveld
Dr. Patrick Groenveld. Patrick has worked at Magma, Cadence, Synopsys and Cerebras, and he lectures at Stanford. He has worked for many years in the EDA industry. He was Chief Technologist at Magma Design Automation where he was part of the team that developed a groundbreaking RTL-to-GDS2 synthesis product. Patrick was also a Full Professor of Electrical Engineering at Eindhoven University. He is a lecturer in the EE department at Stanford University and serves as finance chair in the Executive Committee of the Design Automation Conference. Patrick received his MSc and PhD degrees from Delft University of Technology in the Netherlands.
Hao-Chung Kuo
Chair Professor, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
Director, HHRI, Semi Research
Prof. Hao-Chung Kuo received the B.S. degree in physics from the National Taiwan University, Taipei, Taiwan, the M.S. degree in electrical and computer engineering from Rutgers University, New Brunswick, NJ, in 1995, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois at Urbana Champaign, Urbana, in 1999.
From 1993 to 1995, he was a Research Consultant in Lucent Technologies, Bell Laboratories, and from 1999 to 2001 he was a Member of Technical Staff in Fiber-Optics Division at Agilent Technologies. From 2001 to 2002, he was with LuxNet Corporation. Since October 2002, he has been a Faculty Member of the Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan. His current research interests include semiconductor lasers, vertical-cavity surface-emitting lasers, blue and UV LED lasers, quantum-confined optoelectronic structures, optoelectronic materials, and solar cell. He has authored or coauthored more than 400 journal papers and holds 45 granted and 10 pending patents.
Prof. Kuo’s service to the III-V community is multifaceted. He was elected as the Chairman of IEEE/Photonics Taipei Chapter (since 2012). In addition, he was in the Technical Program Committee for several major technical conferences for the IEEE, the OSA, and the SPIE, which include IEEE/OSA CLEO (2009 – Present), SPIE Photonics West (2009 – Present), and others. He serves as a Panel Member for Taiwan National Science Council (Photonic Program- especially in semiconductor lasers and LEDs). He was the Guest Editor of the IEEE JSTQE (2009) and was an Associate Editor of the OSA/IEEE Journal of lightwave technology (2008-2013) and Associate Editor of the OSA Photonics Research (2019-now). He was the recipient of The Optical Engineering Society of Taiwan (SPIE Taipei Chapter) – Young Researcher Award in 2007. NSC of Taiwan- Dr. Ta-You Wu Award in 2007. Faculty Research Award of NCTU in 2010, 2011. Micro-optics Conference (MOC) Contribution Award-10th MOC Program-committee Chairman (2011). He was recognized by the Photonics community and received OSA(2011), IET (2011), SPIE (2012) IEEE (2015) Fellow.
Dr Li Yisuo
Unisantis Electronics Singapore Pte Ltd
Li is a semiconductor veteran with 24 years’ TCAD experience. He worked with Globalfoundries, Synopsys, Global TCAD and he was Co-Founder of Cogenda. From 2008 he joined Unisantis and led 32nm ~ 1.5nm technology node Surrounding Gate Transistor research developing. Now he shifted to floating body memory research.
Li holds 46 patents covering memory, power device and advance logic. He actively supports simulation pragmatism and chase the perfect silicon proven TCAD. Li has many publications, e.g. in 2021, he published 1st 1.5nm node SRAM paper in IMW.
As a developer, Li codes with C++, python and java script mainly.
Dr. Guichard will provide an update on Silvaco TCAD Victory simulation products, the importance of TCAD in the development of next-generation devices, and the future of TCAD development.
Dr Eric Guichard, SVP and GM of TCAD Business Unit
Silvaco, Inc.
Eric Guichard, Ph.D., has served as Silvaco’s Senior Vice President and General Manager of TCAD Business Unit since November 2012, and as Silvaco’s Vice President of Applications from July 2008 to November 2012. From September 1995 to July 2008, Dr. Guichard served in various roles with Silvaco SA, formerly known as Silvaco Data Systems, one of Silvaco’s wholly-owned subsidiaries, including as an applications engineer. Dr. Guichard received a M.S. in material science and a Ph.D. in semiconductor physics from Institut Polytechnique de Grenoble, France.
Large amount of research efforts was invested in the last two decades in wideband gap GaN based lateral power devices, which are currently approaching commercial maturity for power electronic switching up to 650 V class. Yet, they do not approach their theoretical material limit, in terms of RDS_ON × A vs. VBr. Among the reasons for this limitation are trade off between the blocking strength and the increase of dispersion and the vertical blocking strength of GaN on Si substrates. Among the different approaches to overcome these challenges, two device technologies may be pointed out; vertical GaN based devices and ultra-wideband gap lateral HFET with AlN buffer. Vertical GaN based transistors are desired due to their reduced wafer “foot print”, in comparison to lateral HFETs, that results in a reduction of RDS_ON × A by one order of magnitude down to 1.0 m∙cm2. In addition, the possibility of strain free homoepitaxy allows the growth of thick drift layers with low residual background doping for blocking capability larger than 1 kV. Lateral GaN based transistors (HFETs) with un-intentional doped AlN as buffer material and with high conduction band offset at the AlN-buffer / GaN channel interface should effectively confine the GaN transistor channel. This will result into blocking strength enhancement and low dispersion effects.
Physical based simulation tools are essential for the development and insight to these new generation of wide band gap electronic devices in FBH laboratories. In this talk, we will give examples for the use of “Silvaco” simulation tools used to design, predict and analysis the electrical characterization of vertical and lateral GaN based power devices. The conductance properties of GaN based fin MISFETs are explored and compared to experimental characteristics. The conductance properties are predicted with the variation of geometrical dimensions and the epitaxial layers properties. Edge termination topologies in vertical GaN devices are engineered using avalanche models and compared to experimental and theoretical values. Finally, insight to trapping and de trapping effects AlN / GaN lateral HFET gives explanation to dynamic ON state resistance peculiarity using avalanche model specific to the device epitaxial structure.
Dr. Eldad Bahat-Treidel, Senior Scientist
Ferdinand-Braun-Institut (FBH)
Eldad Bahat-Treidel received his B.Sc. degree in chemical process engineering and M.Sc. degree in electro-optic engineering from Ben Gurion University, Be’er Sheva, Israel in 1996 and 2004 respectively. He received his Ph.D. ( Dr. Ing. ) in electrical engineering from the Technische Universität Berlin Germany in 2012. In 1996 he joint Intel electronics LTD as a photolithography critical layers process engineer, and then joined in 2004 Tower semiconductor LTD as a senior research and development photolithography engineer. In 2006 he joined the Ferdinand-Braun-Institut gGmbH, Leibniz-Institut für Höchstfrequenztechnik (FBH) in Berlin for the development GaN switching transistors for high voltage power electronics applications. Since 2014 he is working on the research and development of innovative electronic devices such vertical GaN based transistors.
In his presentation to Silvaco’s User Group, Debo will introduce Kepler Computing, talk on why Kepler was formed, what the company is doing to enable Design Beyond CMOS, particularly for memory applications, and the use of Silvaco TCAD to simulate these new memories.
Debo Olaosebikan, Co-Founder and CEO
Kepler Computing
Debo is an entrepreneur, physicist and engineer based in San Francisco who, prior to Kepler, was Co-Founder and Chief Technology Officer of Gigster. He was a physics PhD candidate at Cornell University, where he was lead researcher from Cornell working to build an electric silicon laser. He researched spintronics at IBM Almaden and was the Future Africa Awards – Best Use of Science Winner in 2011. Debo invests and advises startups and was a mentor at the Thiel Fellowship.
To achieve the power, performance, and area (PPA) goal in modern semiconductor design, the trend to go for More-than-Moore heterogeneous integration by packing various components/dies into a package or a PCB becomes more obvious as the economic advantages of More-Moore scaling for on-chip integration are getting smaller and smaller. In particular, we already encounter the high cost of moving to more advanced technology and the high fabrication cost associated with EUV, mask, process, design, EDA, etc. Heterogeneous integration refers to integrating separately manufactured components into a higher-level assembly (such as System-in-Package, SiP, and even multiple packages in a PCB) that provides enhanced functionality and improved operating characteristics. Unlike the on-chip designs with relatively regular components and wirings, the layout design problem for heterogeneous integration often needs to handle arbitrary component/board shapes, diverse metal line widths, and different spacing requirements between components, wire metal, and pads, with multiple cross-physics domain considerations such as system-level, physical, electrical, mechanical, thermal, and optical effects, which are not well addressed in the traditional chip design flow. In this talk, we first introduce popular heterogeneous integration technologies and options, their layout modeling, and induced layout design automation problems, survey key published techniques, and provide some future research directions for modern layout design problems for heterogeneous integration.
Professor Yao-Wen Chang, Distinguished Professor & Dean
College of EECS, National Taiwan Univ.
Yao-Wen Chang received a B.S. degree from National Taiwan University (NTU), Taiwan, in 1988, and M.S. and Ph.D. degrees from the University of Texas at Austin in 1993 and 1996, respectively, all in computer science.
Dr. Chang is a Fellow of the ACM and the IEEE. He is currently the Immediate Past President of the IEEE Council on Electronic Design Automation (CEDA) after serving as the first non-US/-European CEDA president in 2020/2021. He is currently the Dean of the College of Electrical Engineering and Computer Science (EECS) and a Distinguished Professor of the Dept. of Electrical Engineering of NTU. He was Deputy Vice President for Academic Affairs of NTU 2016-2018, Associate Dean of the College of EECS 2012-2016, and the Chairman of the Graduate Institute of Electronics Engineering 2010-2013. Dr. Chang was a visiting professor at Waseda University in Japan 2005–2010 and a visiting scholar at the Computer Science and Artificial Intelligence Laboratory (CSAIL) of Massachusetts Institute of Technology (MIT) in 2014. His current research interests lie in electronic design automation. He has co-authored one textbook on Electronic Design Automation (934 pages; Elsevier/Morgan Kaufmann, 2009) and one research book on routing (Springer, 2007), 17 U.S. patents, and more than 360 ACM/IEEE conference/journal papers in these areas (91 papers in DAC [#1 worldwide], 77 papers in ICCAD [#2 worldwide], and 83 papers in TCAD [#3 worldwide]), including highly cited works on floorplanning, placement, routing, design for manufacturability, and FPGA. He published the world’s most DAC+ICCAD+TCAD papers. His NTUplace3 placer was the core engine of the popular Digital Custom Placer of SpringSoft, acquired by the #1 EDA vendor, Synopsys, in 2012 for USD 400M+, and his NTUplace4 received three champions at top EDA contests, and is the core engine of the current leading macro placer, MaxPlace, by Maxeda, acquired by Synopsys in 2023. He was ranked #1 worldwide among 40K+ researchers by the Microsoft Academy for Recent Five-Year Citations in the Hardware and Architecture Domain 2011—2012 before the system retired. He was among the top-2% of scientists named by Stanford University.
Dr. Chang received four awards at the 50th ACM/IEEE DAC in 2013 for the DAC Prolific Author Award (then 40 Club; now 91 papers, the all-time #1 prolific author), 1st Most Papers in the 5th Decade (34 DAC papers in the 5th decade; #1 worldwide; still #1 in the 6th decade with 50 papers), Most Prolific Author (at least 6 papers) in a Single Year (2012, 2013, 2020, 2022, and 2023), one of the Longest Publication Streaks (15 years from 1999 to 2013; 25 years from 1999 to now, #1 worldwide). Dr. Chang is a 1st-place winner of seven major ACM/SIGDA and/or IEEE/CEDA-sponsored EDA Contests and has received 22 top-3 such contest awards (worldwide #1). He is a recipient of eleven Best Paper Awards (including the 2017 DAC Best Paper Award), the 2007 IEEE/ACM ICCAD Professor Margarida Jacome Memorial Award, and the 2020 IEEE/ACM ASP-DAC Prolific Author Award. He has received 28 Best Paper Award Nominations from top international conferences, including DAC (6 times), ICCAD (5 times), and ISPD (5 times). He has received many awards, such as the 2023 Electrical Engineering Medal from the CIEE (the highest honor from the society), the 2021 Academic Award from the Ministry of Education, the 2023 Distinguished Research Fellow (highest honor) and 2007, 2010, and 2013 Distinguished Research Awards and the 2004 Dr. Wu Ta You Memorial Award, all from the National Science and Technology Council (NSTC) of Taiwan, and 2010, 2012, and 2013 IBM Faculty Awards, the 2022 Y. Z. Hsu Science Chair Professorship, the 2020 Distinguished Research Award from the Pan Wen Yuan Foundation, 2017 TECO Award, the 2018 Micron Teacher Award, the 2009 Distinguished EE Professor from the CIEE, the 2004 MXIC Young Chair Professorship from the MXIC Corp, and the 2014 MXIC Chair Professorship from NTU, and distinguished teaching awards (twice for 10 years, the highest honor for top 1% teachers)/excellent teaching awards (nine times) from NTU.
Dr. Chang has served as an associate editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Transactions on VLSI Systems (TVLSI), IEEE Design & Test of Computers, etc. He has served as the steering committee/general/program chair of ISPD, general/program chair of ICCAD, and program chair of ASP-DAC and FPT, and on the IEEE CEDA, DAC, and ICCAD Executive Committees, the ASP-DAC Steering Committee, and the technical program committees of all major EDA conferences. He has served as CEDA President (2020/2021), President-elect (2018/2019), and Vice President of Conferences (2016/2017) and Technical Activities (2014/2015). He is a recipient of the 2015 IEEE CEDA Outstanding Service Award and the 2012 ACM Recognition of Service Award. He serves on the IEEE Robert N. Noyce Medal Committee (the highest honor in semiconductor) 2022-2024. He has served as the chair of the EDA Consortium of the Ministry of Education of Taiwan and an independent board director of Genesys Logic, Inc, a technical consultant of MediaTek Inc., RealTek Semiconductor Corp., and Faraday Technology Inc. He was a co-founder of Maxeda Technology, a profit-earning provider of the leading macro placer, MaxPlace, invested by MediaTek and Raydium and acquired by Synopsys in 2023.
Dr Lakshmi Kanta Bera
Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore
L. K. Bera is a Senior Principal Scientist specializing in process integration for SiC power MOSFET. He obtained his PhD degree in high mobility strained-Si/SiGe heterostructure MOSFETs from Indian Institute of Technology, Kharagpur, India. Since 2001-2006 he was developing strained channel RFCMOS, nanowire based gate-all-around MOSFETs, High K/Metal gate stacks for advanced CMOS applications at IME. He has previous experience at Silterra and Charted Semiconductor, where he was responsible to device design for 40 nm logic with I/O 1.8V and 1.5V devices. From 2009 to 2021, he was involved in the development of early-stage GaN on Si, GaN on sapphire based HEMT and LED devices as well as NIL process for sensors and photonic devices. He has published more than 100 technical articles, 19 patents and co-author of a book. He is the recipient of IEEE Electron Devices Society (EDS) George E. Smith Award.
ASM-HEMT is an industry standard compact model for Gallium Nitride (GaN) radio-frequency (RF) and power devices.
This talk will cover details of ASM-HEMT including the core formulations and the numerous device effects included in this model.
Successful examples of models developed for commercial RF and power applications with ASM-HEMT will be presented.
The latest advancements in ASM-HEMT model will also be briefly discussed.
Prof. Sourabh Khandelwal, Associate Professor
Macquarie University
Prof Khandelwal is the lead author of two industry standard models: ASM-HEMT for GaN HEMTs and ASM-ESD for ESD diodes. He has published over 100 research papers and three books on various topics on device modeling and circuits simulations.
Viso is a next generation parasitics analysis solution that quickly analyzes the electrical properties of RC parasitic networks, which can crucially impact circuit behavior. Viso’s parasitics-focused approach enables fast analysis of interconnects to pinpoint problem areas. Viso provides a highly intuitive user interface to highlight problematic parasitics, timing estimation and accurate comparison of different extracted netlists.
In this session we will demonstrate the power and capabilities of Viso in a real-world circuit design.
Ayoub Hagrou, Analog Design Engineer
STMicroelectronics
Ayoub Hagrou works as Analog Design Engineer for STM32 General Purpose Microcontroller Products in the MDG division of STMicroelectronics.