Layout Design Automation for Heterogeneous Integration
To achieve the power, performance, and area (PPA) goal in modern semiconductor design, the trend to go for More-than-Moore heterogeneous integration by packing various components/dies into a package or a PCB becomes more obvious as the economic advantages of More-Moore scaling for on-chip integration are getting smaller and smaller. In particular, we already encounter the high cost of moving to more advanced technology and the high fabrication cost associated with EUV, mask, process, design, EDA, etc. Heterogeneous integration refers to integrating separately manufactured components into a higher-level assembly (such as System-in-Package, SiP, and even multiple packages in a PCB) that provides enhanced functionality and improved operating characteristics. Unlike the on-chip designs with relatively regular components and wirings, the layout design problem for heterogeneous integration often needs to handle arbitrary component/board shapes, diverse metal line widths, and different spacing requirements between components, wire metal, and pads, with multiple cross-physics domain considerations such as system-level, physical, electrical, mechanical, thermal, and optical effects, which are not well addressed in the traditional chip design flow. In this talk, we first introduce popular heterogeneous integration technologies and options, their layout modeling, and induced layout design automation problems, survey key published techniques, and provide some future research directions for modern layout design problems for heterogeneous integration.
Professor Yao-Wen Chang, Distinguished Professor & Dean
College of EECS, National Taiwan Univ.
Yao-Wen Chang received a B.S. degree from National Taiwan University (NTU), Taiwan, in 1988, and M.S. and Ph.D. degrees from the University of Texas at Austin in 1993 and 1996, respectively, all in computer science.
Dr. Chang is a Fellow of the ACM and the IEEE. He is currently the Immediate Past President of the IEEE Council on Electronic Design Automation (CEDA) after serving as the first non-US/-European CEDA president in 2020/2021. He is currently the Dean of the College of Electrical Engineering and Computer Science (EECS) and a Distinguished Professor of the Dept. of Electrical Engineering of NTU. He was Deputy Vice President for Academic Affairs of NTU 2016-2018, Associate Dean of the College of EECS 2012-2016, and the Chairman of the Graduate Institute of Electronics Engineering 2010-2013. Dr. Chang was a visiting professor at Waseda University in Japan 2005–2010 and a visiting scholar at the Computer Science and Artificial Intelligence Laboratory (CSAIL) of Massachusetts Institute of Technology (MIT) in 2014. His current research interests lie in electronic design automation. He has co-authored one textbook on Electronic Design Automation (934 pages; Elsevier/Morgan Kaufmann, 2009) and one research book on routing (Springer, 2007), 17 U.S. patents, and more than 360 ACM/IEEE conference/journal papers in these areas (91 papers in DAC [#1 worldwide], 77 papers in ICCAD [#2 worldwide], and 83 papers in TCAD [#3 worldwide]), including highly cited works on floorplanning, placement, routing, design for manufacturability, and FPGA. He published the world’s most DAC+ICCAD+TCAD papers. His NTUplace3 placer was the core engine of the popular Digital Custom Placer of SpringSoft, acquired by the #1 EDA vendor, Synopsys, in 2012 for USD 400M+, and his NTUplace4 received three champions at top EDA contests, and is the core engine of the current leading macro placer, MaxPlace, by Maxeda, acquired by Synopsys in 2023. He was ranked #1 worldwide among 40K+ researchers by the Microsoft Academy for Recent Five-Year Citations in the Hardware and Architecture Domain 2011—2012 before the system retired. He was among the top-2% of scientists named by Stanford University.
Dr. Chang received four awards at the 50th ACM/IEEE DAC in 2013 for the DAC Prolific Author Award (then 40 Club; now 91 papers, the all-time #1 prolific author), 1st Most Papers in the 5th Decade (34 DAC papers in the 5th decade; #1 worldwide; still #1 in the 6th decade with 50 papers), Most Prolific Author (at least 6 papers) in a Single Year (2012, 2013, 2020, 2022, and 2023), one of the Longest Publication Streaks (15 years from 1999 to 2013; 25 years from 1999 to now, #1 worldwide). Dr. Chang is a 1st-place winner of seven major ACM/SIGDA and/or IEEE/CEDA-sponsored EDA Contests and has received 22 top-3 such contest awards (worldwide #1). He is a recipient of eleven Best Paper Awards (including the 2017 DAC Best Paper Award), the 2007 IEEE/ACM ICCAD Professor Margarida Jacome Memorial Award, and the 2020 IEEE/ACM ASP-DAC Prolific Author Award. He has received 28 Best Paper Award Nominations from top international conferences, including DAC (6 times), ICCAD (5 times), and ISPD (5 times). He has received many awards, such as the 2023 Electrical Engineering Medal from the CIEE (the highest honor from the society), the 2021 Academic Award from the Ministry of Education, the 2023 Distinguished Research Fellow (highest honor) and 2007, 2010, and 2013 Distinguished Research Awards and the 2004 Dr. Wu Ta You Memorial Award, all from the National Science and Technology Council (NSTC) of Taiwan, and 2010, 2012, and 2013 IBM Faculty Awards, the 2022 Y. Z. Hsu Science Chair Professorship, the 2020 Distinguished Research Award from the Pan Wen Yuan Foundation, 2017 TECO Award, the 2018 Micron Teacher Award, the 2009 Distinguished EE Professor from the CIEE, the 2004 MXIC Young Chair Professorship from the MXIC Corp, and the 2014 MXIC Chair Professorship from NTU, and distinguished teaching awards (twice for 10 years, the highest honor for top 1% teachers)/excellent teaching awards (nine times) from NTU.
Dr. Chang has served as an associate editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Transactions on VLSI Systems (TVLSI), IEEE Design & Test of Computers, etc. He has served as the steering committee/general/program chair of ISPD, general/program chair of ICCAD, and program chair of ASP-DAC and FPT, and on the IEEE CEDA, DAC, and ICCAD Executive Committees, the ASP-DAC Steering Committee, and the technical program committees of all major EDA conferences. He has served as CEDA President (2020/2021), President-elect (2018/2019), and Vice President of Conferences (2016/2017) and Technical Activities (2014/2015). He is a recipient of the 2015 IEEE CEDA Outstanding Service Award and the 2012 ACM Recognition of Service Award. He serves on the IEEE Robert N. Noyce Medal Committee (the highest honor in semiconductor) 2022-2024. He has served as the chair of the EDA Consortium of the Ministry of Education of Taiwan and an independent board director of Genesys Logic, Inc, a technical consultant of MediaTek Inc., RealTek Semiconductor Corp., and Faraday Technology Inc. He was a co-founder of Maxeda Technology, a profit-earning provider of the leading macro placer, MaxPlace, invested by MediaTek and Raydium and acquired by Synopsys in 2023.