It is well known that analyzing LVS reports is often a difficult and brain-teasing task because the “global” nature of connectivity. Unlike DRC reports, where geometrical violations are usually restricted to two shapes, in LVS one must take into account many “widely separated” elements. In addition, quite often a small netlist error will propagate itself in an avalanche manner. Therefore many efforts are directed to localization of LVS errors in Guardian reports, as well as to means of efficient inspection of these reports.

Expert API is intended for customizing and extending the existing software functionality by functions written by the users of Expert using C/C++.

We analyze quantitatively the real impact of technology on the needed level for carrier transport modeling. The results, based on theoretical analyses, are applied to existing devices. This work shows which recipes must be used to evaluate the performances of advanced device architectures (down to 50nm gate length).

The Gate-All-Around SOI transistor [1], in which the gate oxide and the gate electrode are wrapped around the semiconductor region between the source and drain electrodes, exhibits very attractive features [2,3]. This device has been shown to present excellent Ion/Ioff trade-off, good threshold voltage roll-off reduction and better resisting to short-channel effect and DIBL. In this study, based on the self-consistent solution of Schrodinger and Poisson equations, we attempt to show that the maximum of electrons concentration can be located in the middle of the semiconductor film and that there exists
an “optimal” thickness of the Si-film.

The Modella lateral PNP bipolar model was  developed by Philips Electronics N.V. and first released to the public domain in 1990 [1,2]. A release of this model has been implemented within SmartSpice, and can be accessed by setting the LEVEL parameter of the BJT model card to 500.