What’s in the New MIPI Alliance I3C V1.1 Standard?
Mobile devices today contain a rich assortment of sensors that need to communicate their information as quickly as possible at the lowest possible power. To achieve this the MIPI Alliance has gathered industry leaders to create a new interface standard for connecting peripherals and sensors.
I3C has the advantages in reducing pin count, increasing performance, and decreasing power while achieving some level of backwards compatibility with the long-established I2C interface. The new I3C V1.1, announced in January 2020, enables faster interface speeds up to 100 Mhz and has many other new features that will aid the transition from I2C to I3C in applications.
What attendees will learn:
- Background on the development of I3C
- Basic MIPI I3C signaling and protocol
- Comparison of I2C vs I3C
- Key features of I3C
- Lower power
- Hot pluggable
- High Data Rate (HDR) modes
- Dynamic Addressing
- In-band Interrupts
- Common Command Codes (CCCs)
- I3C roadmap features
- Integrating I3C cores
Presenter
Paul Kimelman has been designing and architecting ASIC, boards, and software for 35 years. He holds two Bachelors from University of California at Santa Cruz, one in Computer and Information Sciences, and one in Physiological Psychology. He currently is Platform Architect for Automotive Microcontrollers and Processors at NXP Semiconductors. Before that he was Senior Director of MCU Architecture at NXP, and was previously a Senior Architect at Texas Instruments and at ARM.
Paul has spent most of his career focus on MCUs and deeply embedded systems. Since his architecting of ARM ARMv7-M (Cortex-M), he has focused on Cortex-M based MCUs. He has been an active contributor to the MIPI I3C specification, and won the 2016 Leadership award.
When: February 27, 2020
Where: Online
Time: 10:00am-11:00am-(PDT)
Language: English
WHO SHOULD ATTEND:
Chip architects, engineers, and product managers who are considering incorporating I3C into their next generation products.