Learn How to Simulate 2D-TMD-Channel FETs with Atomistic Precision
Are 2D-TMD-channel transistors suitable candidates for the replacement of silicon ? Considering the extreme scaling down to a few atomic layers of the FET channel, only an atomistic solution looks viable. In this context, we show how the Victory Atomistic tool can answer this essential question thanks to quantum mechanics, offering valuable support for the prototyping effort of a 2D transistor in a professional TCAD environment.
What You Will Learn
- An understanding of the physics and engineering of 2D TMD NR architectures at the atomic scale
- Why to use Atomistic TCAD
- How to simulate and prototype at the atomic level
- Example of a 2D-TMD TFET
Presenter
Dr. Philippe Blaise, Senior Application Engineer, Silvaco, Inc.
Dr. Philippe Blaise has been a senior application engineer in atomistic simulation at Silvaco’s TCAD Division for three years. Prior to joining Silvaco, Dr. Blaise was a senior engineer specialized in atomistic simulation of new memory devices and transistors at CEA/LETI for 15 years. He is a former member of the IEEE IEDM Modelling and Simulation Committee. He is co-author of more than 50 papers in peer-review journals in the field and 30 contributions to conferences and workshops, plus 5 patents and one book chapter.
Dr. Blaise holds a Master’s degree in applied mathematics from ENSIMAG engineering school and a Ph.D. in solid states physics from the Université Grenoble Alpes, France.
WHO SHOULD ATTEND:
TCAD engineers, device engineers, process engineers, product managers, and engineering management.
When: September 26, 2024
Where: Online
Time: 10:00am Santa Clara
Time: 10:00am Beijing
Time: 11:00am Paris
Language: English