Join us at the Design Automation Conference 2025 where we will highlight the company’s wide range of EDA products and semiconductor IP targeting, Power Devices, Automotive, Memory, Displays, HPC, 5G / 6G, and IoT applications.
When: June 23– 25, 2025
Exhibit Hours:
- Monday June 23 – 10:00 AM PDT – 6:00 PM PDT
- Tuesday June 24 – 10:00 AM PDT – 6:00 PM PDT
- Wednesday June 25- 10:00 AM PDT – 4:00 PM PDT
Where: Moscone Center West, Second Floor, Booth 2323, San Francisco, CA
Meet with Silvaco experts to learn about our latest developments and technologies in EDA tools for Analog Custom IC design analysis and verification, automated cell library creation and optimization, and our broad portfolio of design IP.
Theatre Presentations
Stop by our booth and attend one of our technical presentations to learn more about our products.
Everyone who attends one of our presentations will receive a free gift and a raffle ticket.
Prizes include Apple AirPods and the JBL Go 4, an ultra-portable, waterproof, and dustproof Bluetooth speaker. Raffles are held twice daily, so don’t miss your chance to win!
Presentations will cover:
- AI Takes EDA to the Next Level
- Presented by Wally Rhines
- How Low Can You Go? – Low Voltage Requirements at Advanced Nodes
- We will describe the challenges and innovations in ultra-low voltage operation that will enable your next advanced node design.
- Advanced Memory Compiler Solutions for Your Next SoC
- Memory compilers are no longer a nice-to-have in advanced SoC design. We will discuss how a carefully implemented compiler solution will compress your design schedule and accelerate your time to market.
- Accelerate Your SPICE Simulator Performance with Jivaro Pro!
- Accelerate post-layout SPICE simulations up to 15X. Discover how Jivaro Pro can dramatically speed up post-extraction simulations to increase productivity and enable increased coverage. This session will also explore advanced techniques such as guarded/selective reduction.
- Boost Productivity with Automated Cell Library Creation and Optimization
- This talk covers automated cell creation and optimization with CellForge 3D. We’ll demonstrate how CellForge enables rapid exploration of design architecture alternatives – including single or multi-height cells, compound logic cells, and optimized pin placement and track alignment to improve PPA and routing.
- Accelerate Debug, Reduce Cycles with Viso
- In this talk, we will describe how Viso can be used to find and resolve parasitic-induced issues early in the design cycle before they impact tape-out. Learn how Viso streamlines parasitic debug and verification with a powerful suite of features designed to make the process as easy as 1-2-3. From intuitive visualization to automated root-cause analysis, discover how Viso helps you accelerate debug, reduce design iterations, and boost confidence in your final layout.
- Achieve Higher Yield with Smarter Variation Analysis
- Move beyond traditional Monte Carlo approaches to achieve high yields faster. In this talk, you will learn about advanced low- to high- sigma analysis techniques for advanced nodes and low-power technologies.