IBIS Models in SmartSpice

Introduction

The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which is affiliated with the Electronics Industry Alliance (EIA). These models are suitable for high-speed designs of digital systems to evaluate Signal Integrity issues (deformation of electronic signals, cross-talk, power/ground bounce, transmission lines…) on printed circuit boards (PCBs).

The IBIS standard offers a way to provide fast and accurate models of I/O buffers without divulgating any proprietary technology process. As it protects IP, it is now widely used by semiconductor vendors as a replacement for SPICE netlists. The IBIS standard specifies only what kind of information is provided, how this information is presented in ASCII files and how some data are derived from measurements or simulations. How these data are used and processed by a simulator is not part of the standard. The purpose of this documentation is to present the IBIS model support in SmartSpice.

The reader who is not familiar with the IBIS standard or would like to learn more about IBIS may refer to the Web site of the IBIS Open Forum at “http://www.eigroup.org/ibis” where numerous documents are available for download, including introductions, slide shows, articles and complete specifications (from the initial v1.0 to the latest v4.1 of January 2004).