Speaker:

Dr. Babak Taheri, Chief Executive Officer and Board Member
Silvaco, Inc.

Babak Taheri is the CEO and Member of the Board of Directors at Silvaco Group, a leading provider of TCAD, EDA, and design IP software. He began his career at Silvaco as chief technical officer and executive vice-president of products. He also has been the CEO / president of IBT working with investors, private equity firms, and startups on M&A, technology, and business diligence.

While at IBT, he served on advisory boards of MEMS World Summit, Novasentis, AGCM, ALEA labs, Lion Point Capital, and Silver Lake. Prior to IBT, he was the VP & GM of the sensor solutions division at Freescale semiconductor (now NXP).

Babak was the recipient of “The Perfect Project Award” in 2003 while at Cypress; Twice recipient of the “Diamond Chip Award” in 2013 /14 while at Freescale; recipient of the MEMS & Sensors executive of the year award in 2014, and in 2015 was the recipient of the Distinguished Engineering Alumni Medal from UC. Davis College of Engineering, where he is on the advisory board to the college. Dr. Taheri served as a member of the governing council on ESDA Alliance from 2019 to 2021 and served on the board of Parisi House on The Hill from June 2021 to May 2022.

He has held VP/GM roles at Cypress Semiconductors, Invensense (now TDK) and key roles at SRI International and Apple. Babak received his Ph.D. in biomedical engineering from UC Davis with majors in EECS and Neurosciences. He has over 20 published articles and holds over 30 issued patents. His most recent published book in 2021 is titled “Artificial Sensors Shape the Six Pillars of Our Lives”.

Recent Progress of WBG Semiconductor for EV

Speaker:

Hao-Chung Kuo
Chair Professor, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
Director, HHRI, Semi Research

Prof. Hao-Chung Kuo received the B.S. degree in physics from the National Taiwan University, Taipei, Taiwan, the M.S. degree in electrical and computer engineering from Rutgers University, New Brunswick, NJ, in 1995, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois at Urbana Champaign, Urbana, in 1999.

From 1993 to 1995, he was a Research Consultant in Lucent Technologies, Bell Laboratories, and from 1999 to 2001 he was a Member of Technical Staff in Fiber-Optics Division at Agilent Technologies. From 2001 to 2002, he was with LuxNet Corporation. Since October 2002, he has been a Faculty Member of the Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan. His current research interests include semiconductor lasers, vertical-cavity surface-emitting lasers, blue and UV LED lasers, quantum-confined optoelectronic structures, optoelectronic materials, and solar cell. He has authored or coauthored more than 400 journal papers and holds 45 granted and 10 pending patents.

Prof. Kuo’s service to the III-V community is multifaceted. He was elected as the Chairman of IEEE/Photonics Taipei Chapter (since 2012). In addition, he was in the Technical Program Committee for several major technical conferences for the IEEE, the OSA, and the SPIE, which include IEEE/OSA CLEO (2009 – Present), SPIE Photonics West (2009 – Present), and others. He serves as a Panel Member for Taiwan National Science Council (Photonic Program- especially in semiconductor lasers and LEDs). He was the Guest Editor of the IEEE JSTQE (2009) and was an Associate Editor of the OSA/IEEE Journal of lightwave technology (2008-2013) and Associate Editor of the OSA Photonics Research (2019-now). He was the recipient of The Optical Engineering Society of Taiwan (SPIE Taipei Chapter) – Young Researcher Award in 2007. NSC of Taiwan- Dr. Ta-You Wu Award in 2007. Faculty Research Award of NCTU in 2010, 2011. Micro-optics Conference (MOC) Contribution Award-10th MOC Program-committee Chairman (2011). He was recognized by the Photonics community and received OSA(2011), IET (2011), SPIE (2012) IEEE (2015) Fellow.

Experience:
1994-1998 RA, UIUC, USA
1999-2002 MTS HP/Agilent technology, San Jose, USA
2002-2009 Assistant Prof. / Associate Prof. ,NYCU
2009-2011 Director, tsmc, Taiwan
2011-now Prof. / Chair Prof., NYCU
2020- now AVP, Foxconn, Taiwan
2 MOST distinguished research award

TCAD Simulation Update

Abstract:

Dr. Guichard will provide an update on Silvaco TCAD Victory simulation products, the importance of TCAD in the development of next-generation devices, and the future of TCAD development.

Speaker:

Dr Eric Guichard, Senior VP and GM of TCAD Division
Silvaco, Inc.

Dr. Eric Guichard is Vice President of Silvaco’s TCAD Division. He is responsible for managing all aspects of the TCAD division from R&D to field operations. Since joining Silvaco in 1995, he has held numerous positions including director of Silvaco France and most recently Director of Worldwide TCAD Field Operations. Prior to joining Silvaco, Guichard was a senior SOI engineer specializing in transistor and circuit aging at LETI and Thomson Military and Space.

Dr. Guichard holds an MS in material science and a Ph.D in semiconductor physics from Ecole Nationale Polytechnique de Grenoble, France.

Analog Custom Design Update

Abstract:

Thomas Blasei will provide an update on Silvaco’s Analog Custom Design product portfolio, new features and functionality, and the future of Silvaco’s EDA solutions.

Speaker:

Thomas Blaesi, VP and GM of EDA Division
Silvaco, Inc​​​

Thomas F. Blaesi is Vice President and General Manager of the EDA Business Unit. He is responsible for managing the development of all EDA tools including analog customer design, circuit simulation and SPICE modeling. Thomas joined Silvaco in October 2017 and held the position of Vice President of Global Marketing until December 2019. He has more than 25 years of experience in corporate strategy, business development, and marketing in semiconductor, and electronic design automation industries. He has led major projects in SoC platform-based design, system-level design, and design for manufacturing in addition to hands-on experience in custom and semi-custom chip design and development.

Most recently, Thomas was the managing partner at Zeema Technologies. Before that, he served as CEO of Chipvision, and held various senior business and technical positions at Cadence, Synopsys, and LSI Logic.

Thomas holds a BS in electrical engineering and computer science from Hochschule Furtwangen University, Germany.

Design IP Solutions Update

Abstract:

Ben Louie will provide an update on Silvaco’s portfolio of Design IP, and its direction for the future.

Speaker:

Ben Louie, Associate Vice President of Foundation IP​
Silvaco, Inc​​​.

Ben Louie has over 22 years of experience in Memory Design including NOR Flash, NAND Flash, and MRAM. Most recently he was Director of Memory Design and Fellow at Spin Memory where he led their MRAM memory design efforts and was one of the primary inventors for their MRAM Engine IP. Prior to Spin Memory, Ben was Director of Design and Chief Design Engineer at Zeno Semiconductor where he worked on the development of a novel 1T SRAM memory. Additional startup experience also includes Magsil, a Field MRAM IP company. Before working startups, Ben worked at a few large semiconductor companies including Micron Technology and Xilinx. At Micron Technology, Ben led the Design team in the transition from NOR flash to NAND flash and was the design lead/manager for their first NAND products. Ben holds a Bachelor of Science Degree in Electrical Engineering and a Master of Science Degree in Electrical Engineering from Santa Clara University. He has been issued over 116 US Patents.

Latest Update on Interconnect Parasitic Reduction and Analysis with Jivaro and Viso

Abstract:

In this presentation we will present the new features developed in Jivaro (parasitic reduction) and Viso (parasitic analysis and exploration) to tackle various challenges related to post layout interconnect parasitics. Latest Jivaro with its new “Pro” module is taking the parasitic reduction to a new era and enables unprecedented speed of SPICE simulations, especially for advanced process nodes. Viso has been enriched with new features to enable fast understanding and debug of parasitic structures without the need for long simulations.

Speaker:

Simon-Alexis Abric, Corporate Application Engineer
Silvaco, Inc.

Mr. Simon-Alexis Abric is a Corporate Application Engineer for Silvaco France. He is responsible for customer technical support for reduction (Jivaro) and parasitic analysis (Alps) products. Prior to Silvaco, he was an Application Engineer at Edxact SA for four years.

Mr. Abric earned a Master of Engineering degree in integrated circuits and systems in 2013 from the engineering school ENSEIRB in Bordeaux, France.

Advances in Device Modeling Using Utmost IV

Abstract:

In this session Silvaco will present some of the 2022 Baseline enhancements to our Utmost IV Device Modeling tool. We will introduce the Corner and Retargeting Module, the most recent addition to our modeling software platform, and review some of the newest models and technologies where Silvaco’s Utmost IV is a key contributor. The presentation will conclude with a review of Silvaco’s modeling services through which our customers can benefit from our extensive SPICE modeling expertise.

Speaker:

Bogdan Tudor, Senior Manager, Device Characterization
Silvaco, Inc.​

Bogdan Tudor is Head of Device Characterization for Silvaco, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software.

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VarMan Delivers Unprecedented High-Sigma Performance within a User-Friendly GUI Environment

Abstract:

Accuracy and flexibility have always been the core of VarMan technology. Today with the latest GUI redesign and algorithm enhancements, VarMan is entering a new era providing major improvements to the user experience that benefits from a wide customers’ feedback gathered along  years of worldwide deployment.

This new baseline version will be able to keep addressing new challenges and make variation analysis accessible to a larger audience.

Speaker:

Vincent Annezo, VarMan Corporate Application Engineer
Silvaco, Inc​​​.

Vincent is a Corporate Application Engineer dedicated to VarMan improvement and support. Prior to Silvaco, he worked as a Software Validation and Application Engineer at Aselta (French EDA start up) for 9 years. He earned a Master of Engineering degree in physics in 2003 from the engineering school INSA in Rennes, France.

Modern Circuit Placement

Abstract:

A modern chip often contains thousands of pre-designed macros (e.g., embedded memories, IP/analog blocks) and tens of millions of standard cells of very different sizes. The fast-growing design complexity with large-scale mixed-size macros and standard cells gives significant challenges and also opportunities for modern circuit placement. In this talk, we first survey algorithmic paradigms for modern circuit placement and then present key algorithms and machine learning techniques used in modern placers and our NTUplace, which is a three-time champion placer at the DAC, ICCAD, and ISPD placement contests and leads to the leading commercial placer, Maxeda’s MaxPlace. Our placer exemplifies a streamlined integration of analytical, combinatorial, and stochastic algorithms. Finally, we provide some future research directions for modern circuit placement.

Speaker:

Yao-Wen Chang, Dean & Distinguished Professor
College of Electrical Engineering and Computer Science National Taiwan University, Taipei, Taiwan

Dr. Yao-Wen Chang is a fellow of the ACM and IEEE. He received his Ph.D. degree in computer science from the University of Texas at Austin in 1996. He is currently a Distinguished Professor of the Dept. of Electrical Engineering and Dean of the EECS College, National Taiwan University (NTU). His current research interests lie in electronic design automation (EDA). He has co-authored one 934-page textbook on EDA (Morgan Kaufmann, 2009) and one research book on routing (Springer, 2007), 17 U.S. patents, and more than 350 ACM/IEEE conference/journal papers, including highly cited works on floorplanning, placement, routing, design for manufacturability, heterogeneous integration, and FPGA. His NTUplace3 placer was transferred into the popular Digital Custom Placer of Synopsys. His NTUplace4 is a champion circuit placer for the three top contests, DAC, ICCAD, and ISPD, and now the core engine of MaxPlace, the flagship placer of Maxeda and a leading commercial placer. Dr. Chang is the all-time most prolific author in DAC’s 59-year history, also with its longest publication streak (24 years 1999-2022). He received four research awards at the 50th DAC in 2013, eleven Best Paper Awards (including one for the 2017 DAC), and 21 top-3 place contest awards with six champions. He published the world’s most DAC+ICCAD+TCAD papers during the past three decades. He has received many research awards and two distinguished teaching awards for ten years (the highest honor for the top 1% of teachers) and nine excellent teaching awards from NTU.

Dr. Chang has served as the steering committee/general/program chair of ISPD, general/program chair of ICCAD, and program chair of ASP-DAC and FPT, and on the executive/steering committees of ASP-DAC, DAC, and ICCAD. He has been an associate editor of IEEE TCAD, IEEE TVLSI, IEEE D&T, etc. He has served as the IEEE CEDA President, President-elect, and Vice President. Currently, he serves on the IEEE Robert N. Noyce Medal Committee. He is a recipient of the 2015 IEEE CEDA Outstanding Service Award and the 2012 ACM Service Award. He has served as an independent board director of Genesys Logic, Inc, and a technical consultant for MediaTek Inc., Realtek Semiconductor Corp., and Faraday Technology Inc. He is a co-founder of profit-earning Maxeda Technologies, the provider of the leading commercial placer MaxPlace.

Back-End-of-Line Compatible Amorphous Oxide Semiconductor Thin Film Transistor and Numerical Analysis of Oxygen Defects for Monolithic Three-dimensional Integrated Circuit Applications

Abstract:

The back-end-of-line (BEOL) compatible amorphous oxide semiconductor (AOS) thin-film transistor (TFT) is a suitable technology platform for the development of monolithic three-dimensional integrated circuits (M3D-ICs). In this work, n-channel amorphous indium tungsten oxide (a-IWO) nanosheet transistors have been successfully demonstrated in the class of InOx-based TFTs, especially with channel thickness scaling down to 4 nm. The integration of a-IWO nanosheet TFT with HfO2 gate insulator exhibits low operation voltages, good electrical characteristics: near ideal subthreshold swing ~ 63mV/dec., high field-effect mobility ~ 25.3 cm2/V-s. Through TCAD analysis, the effects of oxygen flow during a-IWO thin-film deposition on oxygen interstitials (Oi) defect at the front channel were numerically proved, validating the proposed physical mechanisms with a quantum model for a-IWO nanosheet TFT.

Speaker:

Po-Tsun Liu, Chair Professor,
Department of Photonics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

Prof. Po-Tsun Liu is currently a Chair Professor and Director of Display Research Center at National Yang Ming Chiao Tung University (NYCU) in Taiwan. He is a well-known specialist in TFT and TFT-based functional devices/circuits for TFT-LCDs and AMOLEDs, including amorphous oxide semiconductor (AOS)-based photo-sensors, nonvolatile memory devices (Flash, EEPROM, RRAM) and gate driver on array technologies. Furthermore, he extends the TFT technologies from flat-panel displays to the monolithic 3D-ICs application of advanced semiconductor engineering. He has published over 350 papers in peer-reviewed journals and international conferences, 1 Book and 1 Book chapter editor. He has given more than 100 invited presentations at international and national conferences. Additionally, Prof. Liu was elected IEEE Fellow (2020), SID Fellow (2021) and won the Outstanding Research Award (2021) from National Science and Technology Council (NSTC), in recognition of his unusual distinction in the profession and significant contributions to TFT technologies. He was named on the list of the World’s Top Electronics and Electrical Engineering Scientists (by Research.com). He has also received numerous international conference paper awards, among other national awards in Taiwan, such as the Outstanding Engineering Professor Award from The Chinese Institute of Engineers (2022), Outstanding Electrical Engineering Professor Award from The Chinese Institute of Electrical Engineering in 2015, Excellent Young Scholar Research Grant, The Award for University Special Talents (National Science Council, from 2006-Present).

Prof. Liu’s lectures are always well-received by college students and researchers in FPD industries. For instance, he has won the Outstanding Teaching Award (NCTU, 2019) and has been praised four times by AUO at the annual Teacher’s Day celebrations (2015, 2016, 2018, 2020). Prof. Liu has been always dedicated to contributing himself to the work of scientific research and talent cultivation for many years.

Standard Cells and I/O Library Optimization and Validation

Abstract:

As an active semiconductor foundry, process or technology development and enhancement is frequent. To meet and verify the enhancement on library, library optimization and validation is needed.

In this presentation, we will share the challenges of optimizing and validating different libraries, and demonstrate how Cello, Viola and SmartSpice contribute in a unique, dynamic way to realize the optmization and validation, which ultimately results in reducing library development and validation time even though we have limited man power/resources.

Speaker:

Mr. Faris Amsyar Bin Ahmad Zhaki, IP Staff Engineer
SilTerra Malaysia Sdn. Bhd

Mr. Faris Amsyar Bin Ahmad Zhaki is an IP Staff Engineer with SilTerra focusing on Standard Cell and I/O library development and silicon validation for over 5 years. Mr. Faris Amsyar Bin Ahmad Zhaki holds a Bachelor of Electronics Engineering from University of Science, Malaysia.

Standard Cells and I/O Library Optimization and Validation

Abstract:

As an active semiconductor foundry, process or technology development and enhancement is frequent. To meet and verify the enhancement on library, library optimization and validation is needed.

In this presentation, we will share the challenges of optimizing and validating different libraries, and demonstrate how Cello, Viola and SmartSpice contribute in a unique, dynamic way to realize the optmization and validation, which ultimately results in reducing library development and validation time even though we have limited man power/resources.

Speaker:

Nur Liyana Binti Jasn, IP Staff Engineer
SilTerra Malaysia Sdn. Bhd

Ms. Nur Liyana Binti Jasni is an IP Staff Engineer with SilTerra focusing on Standard Cell and I/O library development and silicon validation for over 11 years. Ms. Nur Liyana Binti Jasni holds a Bachelor of Science in Electronics & Computer Engineering from Hanyang University, South Korea.