Full-Chip Curvilinear Patterning: From Design-Stage Exploration to Process-Variation Analysis

Abstract

Curvilinear mask shapes are moving into production at advanced nodes, and they stress correction, verification, and mask rule checking (MRC) flows built for rectilinear geometry. This webinar presents Silvaco’s production PPC suite as a single connected flow rather than a set of point tools. We start upstream in the PPC Interactive Optimizer, where designers run lithography contour simulation during layout creation, debug hot spots, and test design-rule variants against printability — putting patterning-aware decisions well before tapeout. We then move to full-chip curvilinear correction: main-feature and SRAF generation, with MRC enforced during optimization rather than repaired afterward, and post-correction verification and curvilinear mask rule checks run directly on curvilinear output instead of rectilinear approximations. Finally, we show how PPC feeds the Silvaco FTCO™ (Fab Technology Co-Optimization) intelligence solution platform, turning individual correction runs into structured, reusable engineering data that supports systematic process-variation studies. Worked examples show where each stage cuts iterations between design intent and manufacturable mask data.

What You Will Learn

• How full-chip curvilinear correction, verification, and MRC are handled natively on curved contours
• How PPC integration with Virtuoso enables interactive lithography exploration during layout creation
• How Victory DoE connects PPC into FTCO workflows for systematic process-variation studies

Presenter

Alan Zhu
Director of Engineering, Silvaco

Alan Zhu is the Director of Engineering at Silvaco, where he leads the Process Proximity Compensation (PPC) team covering OPC, RET, verification, and modeling development. He joined Silvaco through the 2025 acquisition of Cadence’s PPC product line, which he had previously led as a software engineering director. He has 30 years of experience in computational lithography and EDA software development.

WHO SHOULD ATTEND:

OPC and mask engineers, computational lithography engineers, layout and design-rule engineers, process integration engineers, TCAD engineers, and engineering management.