Semiconductor Ecosystem Predictions for 2019
The beginning of a new calendar year is the perfect to reflect upon and forecast what lies ahead for the semiconductor design ecosystem. Here are my predictions for semiconductor technology, atomistic CAD, SoC design IP, technology optimization, and six-sigma design:
Semiconductor Technology: We have seen a dramatic rise in the use of new kinds of semiconductor devices for mobile phones, automobiles, Intelligent Edge nodes, smart sensors, big data compute and storage utilizing artificial intelligence, machine Learning, and neuromorphic computing. Both Magneto-Resistive memory (MRAM) and Resistive RAM (ReRAM) technologies will play key roles as well as many optical and chemical sensors. TCAD solutions developers will partner with both memory and sensor technology companies in 2019 to accelerate their technology’s development and adoption in several markets.
Atomistic CAD: We will see the adoption of atomistic TCAD to extend Moore’s law to model and simulate devices such as Nanowires and Nanosheets including sensors and quantum dots that approach a few nm in size. Collaborations with university researchers such as Purdue, and their NEMO suit of tools, will enable successful development of nanoelectronic and nanosensor solutions.
SoC Design IP: We see a new ecosystem being developed by Silicon Catalyst that economically and effectively supports the needs of semiconductor startups. Soc design IP is a critical element. Other companies will follow Silvaco’s donation of its design IP which fills a real hole that has been impeding the success of these startups.
I3C (MIPI I3C, also known as SenseWire) is an emerging industry standard for multidrop serial data buses. I3C is an evolution of I²C, a de facto standard two-pin serial bus widely used for low-speed peripherals and sensors in computer systems and sensor interface. Adoption will accelerate dramatically in 2019 for industrial sensor and IoT applications.
Design Technology Co-Optimization (DTCO): Accurately assessing process variability and yield in circuit performance at the nanometer scale is essential to design reliable circuits. Besides accurate device characterization, a complete layout driven co-optimization simulation solution combining FEOL including TCAD simulation (Process, Device), Spice parameter extraction and Spice simulation with BEOL including 3D parasitic extraction, working under a single cohesive flow is a must have to achieve this goal. As semiconductor companies move to sub 7nm process nodes the adoption of a DTCO solution for nanometer technologies, such as nanowire and nanosheet device architectures, will be essential. DTCO flows will ultimately extend Moore’s’ law by improving circuit performance, reducing power and improving yield across the entire design hierarchy making design, layout and simulation tasks faster and simpler.
Six-sigma Design and Variability: With the need for high reliability electronics in automotive market (e.g., Advanced Drivers Assistance System or ADAS), Industrial markets (e.g., robotics), and Mil/Aero (e.g., drones) “true six-sigma” simulations are a must have. Given the variability of the latest nanometer technology processes, the adoption of next generation design variability analysis tools will take-off in 2019. True Six-sigma and even seven-sigma requirements are being adopted by manufacturers, asking for ultra-reliable standard cells, IO’s and memory cell operation. Traditional Monte-Carlo simulation will be replaced by new high-sigma simulation solutions.