November 12, 2020
Silvaco Inc., a leading supplier of EDA software and design IP, today announced that it has completed the acquisition of the memory compiler technology and standard cell libraries of Dolphin Design SAS.
Location Atlanta, GA
Silvaco seeks an experienced Application Engineer with a strong background in electrical device measurement and characterization, and in SPICE model extraction. This individual will be responsible for providing support to our Utmost IV modeling tool customers and performing SPICE modeling services.
In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation.
In this paper the critical design features of a SiC superjunction trench MOS device were optimized using CAD to obtain a high breakdown voltage while minimizing any unnecessary increase in channel resistance.
Conductive Bridge Random Access Memory (CBRAM) is a non-volatile memory device technology that can operate by consuming very low power. Another advantage of the CBRAM devices is its ability to be easily integrated into conventional back-end-of-line CMOS processes [1].
The qualification of GaN power high-electron-mobilitytransistors (HEMTs) must consider the device ruggedness against out-of-SOA (safe operating area) events [1- 3].
Dry etching is commonly used in semiconductor processing to generate deep trenches with good anisotropy. Dry etching is applied to many semiconductor technologies including Advanced FinFETs, 3D NAND, and vertical Silicon and Silicon Carbide power devices.
September 9, 2020
September 17, 2020 | 13:00 – 13:30 (JST)
The accuracy of rule-based full-chip parasitic capacitance extraction tools including Silvaco’s Hipex is highly dependent on the description of the rule files.
October 13, 2020 | 10:00 am – 10:30 am (PST)
As computation requirements continue to build and memory systems are operating at ever higher frequencies, high-performance memory subsystems that consume minimal power consumption and small silicon area are a necessary requirement.