Improvement of Parasitic Capacitance Extraction Rules for Large-Scale Layout and Its Accuracy Verification Method
The accuracy of rule-based full-chip parasitic capacitance extraction tools including Silvaco’s Hipex is highly dependent on the description of the rule files. This webinar will show the effectiveness of the newly added pattern-matching models to improve accuracy and the efficient accuracy verification methods using Clever, our 3D field solver, and Belledonne, our netlist comparison tool.
What attendees will learn:
・Overview of rule-based parasitic extraction tool operation
・Measures to improve Hipex rules
・How to check the parasitic capacitances using the netlist comparison tool Belledonne
Yusuke Ito is an Analog Custom Design (ACD) Senior Application Engineer at Silvaco Japan. Since joining Silvaco Japan in 2015, he has been responsible for supporting layout design and verification tools, and in 2019 he is honored “AE to Go Above and Beyond to Solve a Customer Issue” for his customer service as recognized one of the best AEs in Silvaco. Prior to joining the company, he was engaged in layout design and verification of digital hardware macros, and has been involved in the development of various ASICs.
WHO SHOULD ATTEND:
Designers of analog design and layout engaging in the parasitic extraction
When: September 17, 2020
Time: 13:00-13:30 – (JST)