日志 Erick Castellon

Generic Devices – The New HIPEX-NET Feature for Extraction of Custom Devices

9月 1, 2004在： /通过：

Hipex-NET is SILVACO’s powerfull hierarchical layout netlist extractor. Built-in extracting rules permit to make fast and accurate parameter extraction for basic set of devices as MOS, BJT, diode, capacitor and resistor. But these rules can’t descibe all devices features and parameters that appeare in new submicron or RF layout designs. To resolve this problem the new HIPEX-NET command HIPEX GENERIC_DEVICE has been introduced. This new HIPEX-NET feature gives to user the capability to extract not only additional parameters for standard devices but also custom defined devices with arbitrary set of parameters. This article describes the new HIPEX-NET command.

Electrostatic Effect of Localized Charge in Dual Bit Memory Cells with DiscreteTraps

8月 1, 2004在： /通过：

In this paper the electrostatic impact of Channel Hot Electron (CHE) injection in discrete-trap memories is quantitatively addressed. The dual bit behavior of the transfer characteristic during forward and reverse read of a written cell is thoroughly analysed with the help of an analytical model. Such model allows, for the first time, to estimate the effective charged portion of the discrete storage layer, L2, and the quantity of electrons, Q, injected in the trapping

Simulating Selective and Non-Selective Epitaxy over Oxide Isolated Regions Using Athena

8月 1, 2004在： /通过：

In certain cases, most notably in modern bipolar and SiGe HBT structures, epitaxial steps are performed after the oxide isolation structures have been already created. Thus the initial surface prior to epitaxy may contain regions of crystalline silicon, polysilicon or insulators, usually silicon dioxide. In the case of LOCOS isolation, the surface is also non-planar. In such epitaxial cases, epitaxy can be divided into two general types:-

HiSIM-1.2 Parameter Extraction with the Revised UTMOST-III Local Optimization Strategies

7月 1, 2004在： /通过：

HiSIM-1.2 parameter extraction methodology was discussed in detail in a previous issue of Silvaco Simulation Standard [1]. This article is meant to provide the precise UTMOST-III local optimization strategies to UTMOST-III users who are interested in HiSIM-1.2 parameter extraction. The developed strategies were applied to the actual 90 nm technology devices [2]. The HiSIM-1.2 proved the capability to give the scalable model down to 100 nm from 10 um channel length with no parameter binning.

A Family Portrait of the BSIM Models

7月 1, 2004在： /通过：

1. Introduction

BSIM1, the first model of the BSIM series was released about ten years ago. Some major improvements have been made since that time, making the BSIM3v3 and BSIM4 models become worldwide standards. This article presents the evolutions brought to BSIM models from BSIM3v3 to BSIM5 and BSIMDG, as well as their applications and differences.

Customers are starting to use 64bit machines with large hard drives and Gigs of RAM

7月 1, 2004在： /通过：

Customers are starting to use 64bit machines with large hard drives and Gigs of RAM and tend to forget the limitations imposed by a 32bit operating system. If you have more than 2Gigs of RAM in a system the extra is not used by the 32bit compiled program as it is not possible to address a contigeous memory space bigger than this when you have 1 parity bit and 31 data bits (2^31). If you are however using our 64bit compiled version of SmartSpice then you can use as much memory (RAM) as you care to put into the system (2^63 is a huge number compared to the 32 bit case).