1. Introduction
BSIM1, the first model of the BSIM series was released about ten years ago. Some major improvements have been made since that time, making the BSIM3v3 and BSIM4 models become worldwide standards. This article presents the evolutions brought to BSIM models from BSIM3v3 to BSIM5 and BSIMDG, as well as their applications and differences.
Customers are starting to use 64bit machines with large hard drives and Gigs of RAM and tend to forget the limitations imposed by a 32bit operating system. If you have more than 2Gigs of RAM in a system the extra is not used by the 32bit compiled program as it is not possible to address a contigeous memory space bigger than this when you have 1 parity bit and 31 data bits (2^31). If you are however using our 64bit compiled version of SmartSpice then you can use as much memory (RAM) as you care to put into the system (2^63 is a huge number compared to the 32 bit case).
Expert’s Node Probing is powerful tool for inspection of netlist components on layout. It is designed for highlighting layout objects electrically connected with each others.
The additional features of Node Probing have been added in the new QT version of Expert. Because the layout extraction is being performed by hierarchical Guardian LPE, the user has possibility to get hierarchical node names troughout node tracing. The original net name in cell instance is keeping and is displaying aditionally to net name from top cell.
Overview
To extract parasitic capacitances from a circuit layout, you need to perform the following steps:
Expert layout editor version 4.0.1R has several new commands and functions released together with the new Qt GUI interface. Most of them are developed in order to improve easier operation.
Q. Every time I create a new project or library, an empty cell with the same name is created in my project. What do I need to setup to avoid the creation of this empty cell?
SILVACO has recently released a new suite of interconnect analysis tools to meet the demands of state of the art cell, circuit and chip design.
On the cutting edge of LSI design, the accuracy of Layout Parasitic Extraction (LPE) tools is a critical issue to miniaturized LSI design of rules measuring 0.13 um or lower. The quantitative consideration of coupling capacitance based on three-dimensional calculation is indispensable. Conventional advanced LSI design tools and methodology are limited in their ability to optimize the LPE library. As a result, the discussion of LPE tool accuracy and extracted parasitic results lack significant quantitative generality.
When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers, convergence can be a real problem. Previous methods suggested in the hints and tips archive of Silvaco’s simulation standard have made use of Silvaco’s Luminous module where a small amount of light intensity is incident on the device, the idea being to generate a small amount of carriers to aid convergence.
Expert Parametric Wire (Pwire) is a complex group of objects containing, a single wire named master wire, any number of subparts such as enclosure wires, offset wires and sets of rectangles. Pwire objects enable extremely quick and efficient creation and editing of guard rings and shielded paths which are increasingly important due to higher integration density of IC designs.