日志 Erick Castellon

Transient Simulations of Edge Emitting Fabry-Perot InP/InGaAsP Laser Diode Using Silvaco TCAD Tools

11月 1, 2004在： /通过：

In this communication we present a brief description of our initial results of transient simulation of InP/InGaAsP Fabry-Perot edge emitting laser diode structure Using Silvaco ATLAS/Blaze and Laser modules. The data presented here have not been optimized and it represents work in progress. This initial simulation presented here represents a heterostructure of bulk materials without any quantum confinement calculations or strain effects. This naturally will impact on the calculated lasing frequency.

Two-Dimensional Device Simulation of the InGaAs/InP Avalanche Photodiodes

11月 1, 2004在： /通过：

The high gain, and high gain-bandwidth product of the avalanche photodiodes is one of the key device for the long distance optical communication systems. For the 0.92-1.65um wavelength range, the narrow bandgap materials, like InGaAs(0.77eV), are used as the absorption medium. And the breakdown location is a major issue to design of the APD’s. In order for the device to operate with high gain and low noise[1], the design of the guard ring to suppress edge breakdown is important.

Resistor and Capacitor L/W Parameters in LVS Comparison

11月 1, 2004在： /通过：

In the design of VLSI circuits the situations occur very often when a single schematic device is implemented in the layout by the group of several devices connected in parallel or series. Such groups of devices must be reduced to a single device in the layout and the circuits must be compared in terms of the single devices taking into account their geometrical characteristics. In this article we introduce some methods of calculation and comparison of geometrical parameters of resistors and capacitors connected in parallel or series, when LVS verification is performed.

A Sophisticated Verilog-A Debugger

10月 1, 2004在： /通过：

During the elaboration of a Verilog-A model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model. The SILVACO Verilog-A debugger has been designed to meet these needs. It is available since version 2.6.0.R of SmartSpice and works along with SILVACO C-Interpreter. It allows iteration-per-iteration Verilog-A modules debugging. The debugger is tracing all the Verilog-A instantiations of the design, either instances of the SmartSpice netlist or in other Verilog-A modules.

Hipex-CRC Parasitic RC-Network Reducer

9月 1, 2004在： /通过：

Design of large scale chips requires precise knowledge of interconnect delays. However, detailed analysis of interconnects may quickly become computationally too expensive due to the distributed nature of the networks, and the large number of internal nodes extracted.