Analog Custom Design Application Notes
Using Custom PCell Evaluators in Expert OA
Efficient Bus Wiring in Expert
Tips to Make PCells Using Javascript
How to Modify MOSFET PCells for Expert’s Device Link
Enabling Netlist Driven Layout with Standard Cells
Creating LISA Scripts to Automate Layout Operations in Expert
Customizing Expert with New Functions Using LISA
Preserving Parametrized Cells When Translating Competitors’ Layout Database into Expert
Expert’s Calibre RVE Interface for DRC/LVS
Layout Verification in Batch Mode
New Features Facilitate DRC Clean Layout and Parasitic Effect Debugging
New Enhanced Possibilities of Netlist Comparison in Guardian LVS
Using DRC Error Database to Analyze LVL Run Results
A Suggested Approach for Layout Versus Schematic (LVS) Comparison Using Guardian LVS
Logic Gate recognition in Guardian LVS
Well Proximity and STI Stress Effect Parameters Extraction in SmartDRC/LVS
Hipex RC: Accuracy Improvement in Parasitic Capacitance Extraction
Hipex-RC: Virtual Connect Names for Unfinished Nets
Hipex-RC: 7 Techniques for Reducing a RC Netlist
Parasitic Back Annotation for Post Layout Simulation
Central Hipex Database and Improved Hipex-C and Hipex-R Technology Files
Selective RC-extraction Methods in Guardian LPE for Post-layout Circuit Simulations